feat(v2): M4 Memory Manager + Prefetch Engine, real V1 PSRAM backend

Implements M4: memory_manager.v (arbitration/buffering/forwarding/
latency hiding/double buffering, §12) + prefetch_engine.v
(double-buffered tile fetch, §13), sitting on the REAL, UNMODIFIED V1
PSRAM backend chain (int8_memory_access.v -> memory_interface.v ->
psram_controller.v, per §15's explicit mandate not to touch the
controller).

Verified fully end-to-end with Verilator: real neural_processor (M1)
fed entirely by memory_manager, computing against PSRAM-resident X/W
tiles (double-buffered prefetch across up to 5 tiles) and writing its
result back to PSRAM -- checked via an independent PSRAM read-back,
with poison bytes around the operand regions to catch addressing
errors. 3/3 jobs pass (1/3/5-tile configurations).

Three real RTL bugs found and fixed during integration (full
diagnostic trail in errors.log ERR-0006): prefetch_engine had no
single-in-flight-request discipline, letting a queued request corrupt
the bank bookkeeping of a fetch already running; the fix's own
!pf_busy guard had a one-cycle blind spot (pf_busy lags pf_start by a
clock) that needed an explicit !pf_start term; and a state-based mux
for the shared backend port was off by one cycle, silently dropping
the PSRAM result write entirely.

Real synthesis: 0 CHECK problems, 851 LUT4/789 FF/108 CCU2C/0 DSP
(expected, no multiplication in this module). Real place&route (via a
synthesis-only timing harness, needed for the same TRELLIS_IO pin-
budget reason as M2's array): Fmax 165.86 MHz, PASS at 80MHz.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

hardware/v2/docs/ROADMAP.md

@@ -22,8 +22,11 @@ reali, non solo scritto).
       `result_buffer.v`). Tutti inferiscono DP16KD reale (10/10 test,
       6/6 config sintetizzate 0 problemi). Scoperta: il costo BRAM di
       weight_buffer e' guidato da P_IN (larghezza), non da DEPTH.
-- [ ] **M4 — Memory Manager** (`memory_manager.v`, `prefetch_engine.v`),
-      backend PSRAM V1 riusato senza modifiche.
+- [x] **M4 — Memory Manager** (`memory_manager.v`, `prefetch_engine.v`),
+      backend PSRAM V1 riusato SENZA MODIFICHE. End-to-end reale (3/3
+      job PASS) con vero neural_processor + vera catena PSRAM V1.
+      3 bug RTL trovati/risolti (`logs/errors.log` ERR-0006). Fmax
+      165.86 MHz.
 - [ ] **M5 — Neural Director** (`neural_director.v`), scheduling first-free.
 - [ ] **M6 — Dependency Manager** (`dependency_manager.v`), ready/waiting
       queue, dependency counters, wake-up, producer tracking.