michele/FPGA-Neural
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

feat: packed_slot.v, real per-slot sequencer FSM (EXP-0065)

Browse Source 
Promotes EXP-0062's own procedural testbench sequence (prefetch ->
buffer swap -> per-tile gather -> operand streaming -> result
capture) into real synthesizable RTL, wrapping layer_prefetch_ctrl.v
-> layer_weight_buffer.v -> weight_tile_gather.v ->
neural_processor_packed.v behind a 9-state FSM matching
neural_director_packed.v's own per-slot contract.

First run: 4/9 failed, deterministic. Root-caused (not a sequencer
bug): the testbench's own w_base computation wrongly treated it as a
byte address needing *2 conversion; layer_prefetch_ctrl.v expects a
word address directly, and packed_slot.v already passes it through
unconverted to match. Fixed the testbench.

Re-verified: 9/9 PASS, 0 errors, bit-exact results and correct
node_id/result_addr passthrough, entirely self-sequenced (no
testbench-side procedural driving of the sub-modules).

Full writeup in hardware/v2/logs/experiments.log EXP-0065.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
This commit is contained in:
michele
2026-09-17 00:02:35 +02:00
co-authored by Claude Sonnet 5
parent 71600096f9
commit 124a0dbca0
3 changed files with 617 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hardware/v2/logs/experiments.log
+52
View File
@@ -3986,3 +3986,55 @@ N real weight-reuse memory paths (not behavioral stubs) for the first
genuine multi-core system correctness test, THEN (only after that genuine multi-core system correctness test, THEN (only after that
passes) a real multi-core system-level P&R Fmax number -- the number passes) a real multi-core system-level P&R Fmax number -- the number
this whole V3 pivot has been building toward since EXP-0059. this whole V3 pivot has been building toward since EXP-0059.
EXP-0065 -- packed_slot.v: real per-slot sequencer, promotes EXP-0062's
testbench procedure into synthesizable RTL (2026-09-17)
CONTEXT: EXP-0064's own next_action -- neural_director_packed.v only
dispatches job descriptors; something must actually sequence prefetch
-> weight-buffer-swap -> per-tile gather -> operand streaming ->
result capture for each dispatched pair. EXP-0062 proved this sequence
correct PROCEDURALLY (testbench driving each sub-module by hand); this
experiment promotes that same sequence into real RTL, matching the
same "testbench-step becomes synthesizable RTL" pattern weight_tile_
gather.v already established (EXP-0061).
METHOD: new hardware/v3/rtl/packed_slot.v -- wraps layer_prefetch_ctrl.v
-> layer_weight_buffer.v -> weight_tile_gather.v -> neural_processor_
packed.v behind a new 9-state sequencing FSM, presenting exactly the
per-slot contract neural_director_packed.v already expects. Disclosed
scope limits (matches this project's own established precedent, EXP-
0058/0062's "activation path is separate, out of scope" framing):
activations come through a wide, per-tile, combinational stand-in port
(real fetch engine deferred, same spirit as this project's earlier
ideal_memory_model.v staging); no result-writeback engine exists yet
either (result_addr_a/b pass through unused, for a future stage). Every
job re-fetches its layer (no resident-weight-skip optimization --
correctness first). Isolated testbench (hardware/v3/sim/tb_packed_slot.v),
same golden formulas as EXP-0062 (independently reproduced), real SDRAM
controller+model, a simple decode-based activation stand-in memory.
FIRST RUN: 5/9 PASS, 4 FAIL, deterministic (li=0 all correct, li=1
partial, li=2 all wrong). Root-caused via hierarchical signal tracing
(dut.state/pf_busy/w_base_lat) -- NOT a sequencer logic bug: the
testbench's own w_base computation was wrong (`li*WORDS_PER_LAYER*2`,
treating w_base as a byte address needing conversion), while layer_
prefetch_ctrl.v expects a WORD address directly (its own established
convention since EXP-0057) and packed_slot.v already passes w_base
through unconverted to match that -- the stray `*2` pointed every
layer after the first at the wrong SDRAM region. Fixed (removed the
`*2`, matching EXP-0062's own addressing exactly).
RESULT (after fix): 9/9 PASS, 0 errors -- 3 layers x 6 positions (9
pairs), bit-exact results AND correct node_id/result_addr passthrough,
driven entirely by packed_slot.v's own real sequencing FSM (no
testbench-side procedural sequencing of the sub-modules, unlike
EXP-0062).
DECISION: packed_slot.v is genuinely verified. This is the last
missing piece between neural_director_packed.v (EXP-0064, dispatch-
only) and a real multi-core system.
next_action: wire N=2 packed_slot.v instances behind a shared SDRAM
arbiter, driven by neural_director_packed.v, for the first genuine
multi-core system correctness test.
hardware/v3/rtl/packed_slot.v
+304
View File
@@ -0,0 +1,304 @@
`timescale 1ns/1ps
// ============================================================
// V3 -- packed_slot.v: real synthesizable per-slot sequencer, the
// piece that promotes EXP-0062's own PROCEDURAL testbench sequence
// (prefetch -> swap -> job dispatch -> tile-by-tile operand feed ->
// result capture) into real RTL, exactly the same class of promotion
// weight_tile_gather.v already did for the byte-gather step
// (EXP-0061).
//
// Wraps: layer_prefetch_ctrl.v -> layer_weight_buffer.v ->
// weight_tile_gather.v -> neural_processor_packed.v, driven by a new
// sequencing FSM, presenting the external contract neural_director_
// packed.v already expects (job_start/x_base_a/b/w_base/n_tiles/
// node_id_a/b -> job_done/result_data_a/b/result_node_id_a/b).
//
// SCOPE LIMITATION (disclosed, matches this project's own established
// precedent -- EXP-0058/0062's own header comments: "activation data
// ... representing the activation/sliding-window path, which is a
// separate, already-existing memory path not the subject of this
// test"): activations are read through a WIDE, per-tile, combinational
// stand-in port (act_tile_addr_a/b -> act_tile_data_a/b), mirroring
// this project's own earlier ideal_memory_model.v-style staging
// (establish the architectural contract before committing to a
// specific real fetch engine). A real activation fetch engine
// (analogous to weight_tile_gather.v, but for the sliding-window/
// activation path) is a separate, later deliverable, NOT built here.
//
// Also disclosed: no result-writeback engine exists yet either --
// result_addr_a/b are passed through unused, for a future writeback
// stage to consume.
//
// EVERY job re-fetches its layer from SDRAM (no resident-weight-skip
// optimization) -- correctness first; EXP-0057's own measured
// prefetch/reuse PERFORMANCE benefit is a property of the buffer
// being read MANY times per fetch (many reuse positions per Director-
// dispatched pair's own tile loop is NOT what's being reused here --
// see note in the FSM below), not of skipping fetches across
// DIFFERENT Director dispatches; adding that optimization is future
// work, not a correctness requirement.
// ============================================================
module packed_slot #(
parameter DATA_WIDTH = 8,
parameter P_IN = 8,
parameter ACC_WIDTH = 32,
parameter BURST_LEN = 8,
parameter ADDR_WIDTH = 26,
parameter LAYER_BYTES = 128,
parameter BUFADDRW = $clog2(LAYER_BYTES)
)(
input wire clk,
input wire rst,
// ---- Director interface (matches neural_director_packed.v's own
// per-slot output ports exactly) ----
input wire job_start,
input wire [ADDR_WIDTH-1:0] x_base_a,
input wire [ADDR_WIDTH-1:0] x_base_b,
input wire [ADDR_WIDTH-1:0] w_base,
input wire [15:0] n_tiles,
input wire [ADDR_WIDTH-1:0] result_addr_a,
input wire [ADDR_WIDTH-1:0] result_addr_b,
input wire [15:0] node_id_a,
input wire [15:0] node_id_b,
output reg job_done, // one-cycle pulse
output reg signed [DATA_WIDTH-1:0] result_data_a,
output reg signed [DATA_WIDTH-1:0] result_data_b,
output reg [15:0] result_node_id_a,
output reg [15:0] result_node_id_b,
output reg [ADDR_WIDTH-1:0] result_addr_a_out,
output reg [ADDR_WIDTH-1:0] result_addr_b_out,
// ---- activation stand-in port (see header -- real fetch engine
// deferred) ----
output reg [ADDR_WIDTH-1:0] act_tile_addr_a,
output reg [ADDR_WIDTH-1:0] act_tile_addr_b,
input wire signed [DATA_WIDTH*P_IN-1:0] act_tile_data_a,
input wire signed [DATA_WIDTH*P_IN-1:0] act_tile_data_b,
// ---- SDRAM controller port (connects directly, or through a
// shared arbiter for N>1 slots) ----
output wire ctrl_req,
output wire ctrl_wr,
output wire [ADDR_WIDTH-2:0] ctrl_addr,
output wire [16*BURST_LEN-1:0] ctrl_wdata,
output wire [2*BURST_LEN-1:0] ctrl_wmask,
input wire [16*BURST_LEN-1:0] ctrl_rdata,
input wire ctrl_ready,
input wire ctrl_busy
);
localparam S_IDLE = 4'd0,
S_PREFETCH = 4'd1,
S_SWAP = 4'd2,
S_JOBSTART = 4'd3,
S_TILEREQ = 4'd4,
S_TILEWAIT = 4'd5,
S_OPERAND = 4'd6,
S_RESULT = 4'd7,
S_DONE = 4'd8;
reg [3:0] state;
reg [ADDR_WIDTH-1:0] w_base_lat, x_base_a_lat, x_base_b_lat;
reg [15:0] n_tiles_lat;
reg [ADDR_WIDTH-1:0] result_addr_a_lat, result_addr_b_lat;
reg [15:0] node_id_a_lat, node_id_b_lat;
reg [15:0] tcnt;
// ---- layer_prefetch_ctrl.v ----
reg pf_start;
wire pf_busy, pf_done;
wire pf_fill_we;
wire [BUFADDRW-1:0] pf_fill_addr;
wire [DATA_WIDTH-1:0] pf_fill_data;
layer_prefetch_ctrl #(
.DATA_WIDTH(DATA_WIDTH), .LAYER_BYTES(LAYER_BYTES), .BURST_LEN(BURST_LEN), .ADDR_WIDTH(ADDR_WIDTH-1)
) u_pf (
.clk(clk), .rst(rst),
.start(pf_start), .layer_base(w_base_lat[ADDR_WIDTH-2:0]), .busy(pf_busy), .done(pf_done),
.fill_we(pf_fill_we), .fill_addr(pf_fill_addr), .fill_data(pf_fill_data),
.ctrl_req(ctrl_req), .ctrl_wr(ctrl_wr), .ctrl_addr(ctrl_addr),
.ctrl_wdata(ctrl_wdata), .ctrl_wmask(ctrl_wmask),
.ctrl_rdata(ctrl_rdata), .ctrl_ready(ctrl_ready), .ctrl_busy(ctrl_busy)
);
// ---- layer_weight_buffer.v ----
wire [BUFADDRW-1:0] lwb_rd_addr;
wire [DATA_WIDTH-1:0] lwb_rd_data;
reg consume_done;
layer_weight_buffer #(.DATA_WIDTH(DATA_WIDTH), .LAYER_DEPTH(LAYER_BYTES)) u_lwb (
.clk(clk), .rst(rst),
.fill_we(pf_fill_we), .fill_addr(pf_fill_addr), .fill_data(pf_fill_data), .fill_done(pf_done),
.rd_addr(lwb_rd_addr), .rd_data(lwb_rd_data), .consume_done(consume_done),
.active_sel(), .swapped()
);
// ---- weight_tile_gather.v ----
reg tile_req;
reg [BUFADDRW-1:0] tile_base;
wire tile_valid;
wire [DATA_WIDTH*P_IN-1:0] tile_data;
weight_tile_gather #(
.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .BUFADDRW(BUFADDRW)
) u_gather (
.clk(clk), .rst(rst),
.tile_req(tile_req), .tile_base(tile_base),
.tile_valid(tile_valid), .tile_data(tile_data),
.rd_addr(lwb_rd_addr), .rd_data(lwb_rd_data)
);
// ---- neural_processor_packed.v ----
reg job_valid_np;
wire job_ready_np;
reg [1:0] job_activation;
reg signed [DATA_WIDTH-1:0] job_bias;
reg operand_valid;
wire operand_ready;
reg signed [DATA_WIDTH*P_IN-1:0] input_data_a_r, input_data_b_r;
reg [DATA_WIDTH*P_IN-1:0] weight_data_r;
reg tile_last;
wire result_valid_np;
reg result_ready;
wire signed [DATA_WIDTH-1:0] result_data_a_np, result_data_b_np;
wire [15:0] result_node_id_a_np, result_node_id_b_np;
wire [3:0] np_state;
wire np_error;
neural_processor_packed #(
.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ACC_WIDTH(ACC_WIDTH)
) u_np (
.clk(clk), .rst(rst),
.job_valid(job_valid_np), .job_ready(job_ready_np),
.job_node_id_a(node_id_a_lat), .job_node_id_b(node_id_b_lat),
.job_bias(job_bias), .job_activation(job_activation),
.operand_valid(operand_valid), .operand_ready(operand_ready),
.input_data_a(input_data_a_r), .input_data_b(input_data_b_r),
.weight_data(weight_data_r), .tile_last(tile_last),
.result_valid(result_valid_np), .result_ready(result_ready),
.result_data_a(result_data_a_np), .result_data_b(result_data_b_np),
.result_node_id_a(result_node_id_a_np), .result_node_id_b(result_node_id_b_np),
.np_state(np_state), .np_error(np_error)
);
localparam ACT_RELU = 2'd1;
always @(posedge clk) begin
if (rst) begin
state <= S_IDLE;
job_done <= 1'b0;
pf_start <= 1'b0;
consume_done <= 1'b0;
tile_req <= 1'b0;
job_valid_np <= 1'b0;
operand_valid<= 1'b0;
tile_last <= 1'b0;
result_ready <= 1'b0;
job_bias <= {DATA_WIDTH{1'b0}};
job_activation <= ACT_RELU;
tcnt <= 16'd0;
end else begin
job_done <= 1'b0;
pf_start <= 1'b0;
consume_done <= 1'b0;
tile_req <= 1'b0;
case (state)
S_IDLE: begin
if (job_start) begin
w_base_lat <= w_base;
x_base_a_lat <= x_base_a;
x_base_b_lat <= x_base_b;
n_tiles_lat <= n_tiles;
result_addr_a_lat <= result_addr_a;
result_addr_b_lat <= result_addr_b;
node_id_a_lat <= node_id_a;
node_id_b_lat <= node_id_b;
job_bias <= {DATA_WIDTH{1'b0}};
job_activation <= ACT_RELU;
pf_start <= 1'b1;
state <= S_PREFETCH;
end
end
S_PREFETCH: begin
if (pf_done) begin
consume_done <= 1'b1;
state <= S_SWAP;
end
end
S_SWAP: begin
// one settle cycle for layer_weight_buffer.v's own
// do_swap (fill_done_latched already set from
// pf_done above; consume_done pulsed this cycle) --
// matches EXP-0058/0062's own tested sequencing.
job_valid_np <= 1'b1;
state <= S_JOBSTART;
end
S_JOBSTART: begin
if (job_valid_np && job_ready_np) begin
job_valid_np <= 1'b0;
tcnt <= 16'd0;
state <= S_TILEREQ;
end
end
S_TILEREQ: begin
tile_req <= 1'b1;
tile_base <= tcnt[BUFADDRW-1:0]*P_IN[BUFADDRW-1:0];
act_tile_addr_a <= x_base_a_lat + {{(ADDR_WIDTH-16){1'b0}}, tcnt};
act_tile_addr_b <= x_base_b_lat + {{(ADDR_WIDTH-16){1'b0}}, tcnt};
state <= S_TILEWAIT;
end
S_TILEWAIT: begin
if (tile_valid) begin
weight_data_r <= tile_data;
input_data_a_r <= act_tile_data_a;
input_data_b_r <= act_tile_data_b;
tile_last <= (tcnt == n_tiles_lat - 16'd1);
operand_valid <= 1'b1;
state <= S_OPERAND;
end
end
S_OPERAND: begin
if (operand_valid && operand_ready) begin
operand_valid <= 1'b0;
tile_last <= 1'b0;
if (tcnt == n_tiles_lat - 16'd1) begin
result_ready <= 1'b1;
state <= S_RESULT;
end else begin
tcnt <= tcnt + 16'd1;
state <= S_TILEREQ;
end
end
end
S_RESULT: begin
if (result_valid_np) begin
result_data_a <= result_data_a_np;
result_data_b <= result_data_b_np;
result_node_id_a <= result_node_id_a_np;
result_node_id_b <= result_node_id_b_np;
result_addr_a_out <= result_addr_a_lat;
result_addr_b_out <= result_addr_b_lat;
result_ready <= 1'b0;
job_done <= 1'b1;
state <= S_IDLE;
end
end
default: state <= S_IDLE;
endcase
end
end
endmodule
hardware/v3/sim/tb_packed_slot.v
+261
View File
@@ -0,0 +1,261 @@
`timescale 1ns/1ps
// ============================================================
// Isolated correctness test for packed_slot.v -- same golden formulas
// as EXP-0062's tb_np_packed_layer_reuse.v (independently reproduced,
// not shared, per this project's "third oracle" convention), but now
// driving packed_slot.v's OWN real sequencing FSM instead of a
// testbench procedurally driving each sub-module -- confirms the
// promotion from testbench-sequence to real RTL (EXP-0062 -> this)
// preserves bit-exact correctness.
//
// Activation stand-in (see packed_slot.v's own header): a simple
// combinational behavioral memory here, addressed by act_tile_addr_a/b
// (tile-index-based, matching packed_slot.v's own addressing:
// x_base + tile_count), standing in for the real (not yet built)
// activation fetch engine.
// ============================================================
module tb;
localparam BURST_LEN = 8;
localparam ROW_BITS = 13;
localparam COL_BITS = 10;
localparam BANK_BITS = 2;
localparam SDRAM_ADDR_WIDTH = BANK_BITS + ROW_BITS + COL_BITS; // 25
localparam CLK_FREQ_MHZ = 64;
localparam CLK_PERIOD_NS = 1000.0/CLK_FREQ_MHZ;
localparam DATA_WIDTH = 8;
localparam P_IN = 8;
localparam ACC_WIDTH = 32;
localparam ADDR_WIDTH = 26;
localparam N_INPUTS = 128;
localparam N_TILES = N_INPUTS/P_IN;
localparam LAYER_BYTES = N_INPUTS;
localparam WORDS_PER_LAYER = LAYER_BYTES/2;
localparam L = 3; // layers
localparam M = 6; // reuse positions per layer, paired 2 at a time
reg clk = 0;
always #(CLK_PERIOD_NS/2.0) clk = ~clk;
reg rst;
integer cyc;
always @(posedge clk) if (!rst) cyc <= cyc + 1;
// ---- real SDRAM controller + model ----
wire ctrl_req, ctrl_wr;
wire [SDRAM_ADDR_WIDTH-1:0] ctrl_addr;
wire [16*BURST_LEN-1:0] ctrl_wdata;
wire [2*BURST_LEN-1:0] ctrl_wmask;
wire [16*BURST_LEN-1:0] ctrl_rdata;
wire ctrl_ready, ctrl_busy;
wire cke, cs_n, ras_n, cas_n, we_n;
wire [BANK_BITS-1:0] ba;
wire [ROW_BITS-1:0] a;
wire [15:0] dq;
wire [1:0] dqm;
reg wpre_req, wpre_wr;
reg [SDRAM_ADDR_WIDTH-1:0] wpre_addr;
reg [16*BURST_LEN-1:0] wpre_wdata;
reg pre_active;
wire slot_ctrl_req, slot_ctrl_wr;
wire [SDRAM_ADDR_WIDTH-1:0] slot_ctrl_addr;
wire [16*BURST_LEN-1:0] slot_ctrl_wdata;
wire [2*BURST_LEN-1:0] slot_ctrl_wmask;
assign ctrl_req = pre_active ? wpre_req : slot_ctrl_req;
assign ctrl_wr = pre_active ? wpre_wr : slot_ctrl_wr;
assign ctrl_addr = pre_active ? wpre_addr : slot_ctrl_addr;
assign ctrl_wdata = pre_active ? wpre_wdata : slot_ctrl_wdata;
assign ctrl_wmask = pre_active ? {(2*BURST_LEN){1'b0}} : slot_ctrl_wmask;
sdram_controller #(
.CLK_FREQ_MHZ(CLK_FREQ_MHZ), .BURST_LEN(BURST_LEN),
.ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS)
) u_ctrl (
.clk(clk), .rst(rst),
.req(ctrl_req), .wr(ctrl_wr), .addr(ctrl_addr), .wdata(ctrl_wdata), .wmask(ctrl_wmask),
.rdata(ctrl_rdata), .ready(ctrl_ready), .busy(ctrl_busy),
.sdram_cke(cke), .sdram_cs_n(cs_n), .sdram_ras_n(ras_n), .sdram_cas_n(cas_n), .sdram_we_n(we_n),
.sdram_ba(ba), .sdram_a(a), .sdram_dq(dq), .sdram_dqm(dqm)
);
sdram_model #(
.CLK_FREQ_MHZ(CLK_FREQ_MHZ), .ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS)
) u_mem (
.clk(clk), .cke(cke), .cs_n(cs_n), .ras_n(ras_n), .cas_n(cas_n), .we_n(we_n),
.ba(ba), .a(a), .dq(dq), .dqm(dqm)
);
function automatic signed [7:0] weight_byte(input integer li, input integer t);
weight_byte = $signed(8'((li*17 + t*29 + 13) & 8'hFF));
endfunction
function automatic signed [7:0] input_byte(input integer li, input integer pos, input integer t);
input_byte = $signed(8'((li*11 + pos*41 + t*7 + 3) & 8'hFF));
endfunction
task automatic sdram_write_burst(input [SDRAM_ADDR_WIDTH-1:0] word_addr, input [16*BURST_LEN-1:0] data);
begin
@(posedge clk); while (ctrl_busy) @(posedge clk);
wpre_req = 1'b1; wpre_wr = 1'b1; wpre_addr = word_addr; wpre_wdata = data;
@(posedge clk); wpre_req = 1'b0;
while (!ctrl_ready) @(posedge clk);
end
endtask
task automatic preload_sdram_layers;
integer li, bi, wb, tt;
reg [16*BURST_LEN-1:0] burst_data;
begin
for (li = 0; li < L; li = li + 1) begin
for (bi = 0; bi < (LAYER_BYTES/(2*BURST_LEN)); bi = bi + 1) begin
for (wb = 0; wb < BURST_LEN; wb = wb + 1) begin
tt = bi*(2*BURST_LEN) + wb*2;
burst_data[wb*16 +: 16] = {weight_byte(li, tt+1), weight_byte(li, tt)};
end
sdram_write_burst((li*WORDS_PER_LAYER + bi*BURST_LEN), burst_data);
end
end
end
endtask
// ---- activation stand-in: act_tile_addr = x_base + tile_index
// (packed_slot.v's own addressing) -- x_base itself is chosen as
// li*1000 + pos*100 below so a simple decode recovers (li,pos,t) ----
reg signed [DATA_WIDTH*P_IN-1:0] act_data_a, act_data_b;
wire [ADDR_WIDTH-1:0] act_addr_a, act_addr_b;
// act_tile_addr = x_base + tile_index (packed_slot.v's own
// addressing); x_base itself encodes (li,pos) as li*100000+pos*1000
// so tile_index occupies the low 3 decimal digits directly.
// ---- packed_slot.v (DUT) ----
reg job_start;
reg [ADDR_WIDTH-1:0] x_base_a, x_base_b, w_base;
reg [15:0] n_tiles_in;
reg [ADDR_WIDTH-1:0] result_addr_a, result_addr_b;
reg [15:0] node_id_a, node_id_b;
wire job_done;
wire signed [DATA_WIDTH-1:0] result_data_a, result_data_b;
wire [15:0] result_node_id_a, result_node_id_b;
wire [ADDR_WIDTH-1:0] result_addr_a_out, result_addr_b_out;
packed_slot #(
.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ACC_WIDTH(ACC_WIDTH),
.BURST_LEN(BURST_LEN), .ADDR_WIDTH(ADDR_WIDTH), .LAYER_BYTES(LAYER_BYTES)
) dut (
.clk(clk), .rst(rst),
.job_start(job_start), .x_base_a(x_base_a), .x_base_b(x_base_b), .w_base(w_base),
.n_tiles(n_tiles_in), .result_addr_a(result_addr_a), .result_addr_b(result_addr_b),
.node_id_a(node_id_a), .node_id_b(node_id_b), .job_done(job_done),
.result_data_a(result_data_a), .result_data_b(result_data_b),
.result_node_id_a(result_node_id_a), .result_node_id_b(result_node_id_b),
.result_addr_a_out(result_addr_a_out), .result_addr_b_out(result_addr_b_out),
.act_tile_addr_a(act_addr_a), .act_tile_addr_b(act_addr_b),
.act_tile_data_a(act_data_a), .act_tile_data_b(act_data_b),
.ctrl_req(slot_ctrl_req), .ctrl_wr(slot_ctrl_wr), .ctrl_addr(slot_ctrl_addr),
.ctrl_wdata(slot_ctrl_wdata), .ctrl_wmask(slot_ctrl_wmask),
.ctrl_rdata(ctrl_rdata), .ctrl_ready(ctrl_ready), .ctrl_busy(ctrl_busy)
);
// real activation decode: x_base encodes (li,pos) as li*100000+pos*1000;
// act_tile_addr = x_base + tile_index (0..N_TILES-1), so
// tile_index = act_addr % 1000, pos = (act_addr/1000) % 100, li = act_addr/100000
function automatic signed [DATA_WIDTH*P_IN-1:0] act_lookup(input [ADDR_WIDTH-1:0] addr);
integer li_d, pos_d, tidx_d, k;
reg signed [DATA_WIDTH*P_IN-1:0] r;
begin
li_d = addr / 100000;
pos_d = (addr / 1000) % 100;
tidx_d = addr % 1000;
for (k = 0; k < P_IN; k = k + 1)
r[k*DATA_WIDTH +: DATA_WIDTH] = input_byte(li_d, pos_d, tidx_d*P_IN + k);
act_lookup = r;
end
endfunction
always @(*) act_data_a = act_lookup(act_addr_a);
always @(*) act_data_b = act_lookup(act_addr_b);
integer errors, tests;
integer li_i, pp_i;
integer acc_a, acc_b, s_a, s_b, k, tt;
reg signed [DATA_WIDTH-1:0] expected_a, expected_b;
integer wd;
task automatic run_one_pair(input integer li, input integer pos_a, input integer pos_b);
begin
tests = tests + 1;
@(posedge clk);
job_start = 1'b1;
x_base_a = li*100000 + pos_a*1000;
x_base_b = li*100000 + pos_b*1000;
w_base = li*WORDS_PER_LAYER; // WORD address, matching layer_prefetch_ctrl.v's
// own convention (EXP-0057/58/62) and this
// testbench's own preload_sdram_layers addressing
n_tiles_in = N_TILES[15:0];
result_addr_a = 26'h9000 + pos_a;
result_addr_b = 26'h9000 + pos_b;
node_id_a = li[15:8]*8'(M) + pos_a[15:0];
node_id_b = li[15:8]*8'(M) + pos_b[15:0];
@(posedge clk);
job_start = 1'b0;
acc_a = 0; acc_b = 0;
for (tt = 0; tt < N_INPUTS; tt = tt + 1) begin
acc_a = acc_a + (input_byte(li, pos_a, tt) * weight_byte(li, tt));
acc_b = acc_b + (input_byte(li, pos_b, tt) * weight_byte(li, tt));
end
s_a = acc_a; s_b = acc_b;
if (s_a <= 0) expected_a = 0; else if (s_a > 127) expected_a = 8'sd127; else expected_a = s_a[DATA_WIDTH-1:0];
if (s_b <= 0) expected_b = 0; else if (s_b > 127) expected_b = 8'sd127; else expected_b = s_b[DATA_WIDTH-1:0];
wd = 0;
while (!job_done && wd < 2000) begin @(posedge clk); wd = wd + 1; end
if (!job_done) begin
$display("FAIL li=%0d pos_a=%0d pos_b=%0d: TIMEOUT waiting for job_done", li, pos_a, pos_b);
errors = errors + 1;
end else if (result_data_a !== expected_a || result_data_b !== expected_b) begin
$display("FAIL li=%0d pos_a=%0d pos_b=%0d: got_a=%0d got_b=%0d expected_a=%0d expected_b=%0d",
li, pos_a, pos_b, $signed(result_data_a), $signed(result_data_b), $signed(expected_a), $signed(expected_b));
errors = errors + 1;
end else if (result_node_id_a !== node_id_a || result_node_id_b !== node_id_b ||
result_addr_a_out !== result_addr_a || result_addr_b_out !== result_addr_b) begin
$display("FAIL li=%0d pos_a=%0d pos_b=%0d: metadata passthrough mismatch (node_a=%0d/%0d node_b=%0d/%0d addr_a=%0d/%0d addr_b=%0d/%0d)",
li, pos_a, pos_b, result_node_id_a, node_id_a, result_node_id_b, node_id_b,
result_addr_a_out, result_addr_a, result_addr_b_out, result_addr_b);
errors = errors + 1;
end else begin
$display("PASS li=%0d pos_a=%0d pos_b=%0d: a=%0d b=%0d (packed_slot.v real sequencer)",
li, pos_a, pos_b, $signed(result_data_a), $signed(result_data_b));
end
end
endtask
initial begin
errors = 0; tests = 0; cyc = 0;
rst = 1; pre_active = 1'b1;
wpre_req = 0; wpre_wr = 0; wpre_addr = 0; wpre_wdata = 0;
job_start = 0; x_base_a = 0; x_base_b = 0; w_base = 0; n_tiles_in = 0;
result_addr_a = 0; result_addr_b = 0; node_id_a = 0; node_id_b = 0;
repeat(5) @(posedge clk);
rst = 0;
@(posedge clk); while (ctrl_busy) @(posedge clk);
$display("=== preload SDRAM with %0d resident-filter weight sets ===", L);
preload_sdram_layers;
@(posedge clk);
pre_active = 1'b0;
$display("=== packed_slot.v real sequencer: %0d layers x %0d positions (paired) ===", L, M);
for (li_i = 0; li_i < L; li_i = li_i + 1) begin
for (pp_i = 0; pp_i < M; pp_i = pp_i + 2) begin
run_one_pair(li_i, pp_i, pp_i+1);
end
end
$display("=== %0d/%0d tests, %0d errors ===", tests-errors, tests, errors);
if (errors == 0) $display("ALL TESTS PASSED (tb_packed_slot)");
$finish;
end
endmodule