micheleandClaude Sonnet 5
ffc1c7ccfc
Datasheet and pinouts.md updated to the current, real state after today's session: flash #1 was implemented then removed (user's own MHz-over-persistence priority call), the clock-closure table now shows the post-revert, post-DEC-0042 numbers (N_SLOTS=4 @ 64MHz 8/8, worst 64.55MHz/best 72.37MHz; N_SLOTS=8 deferred by explicit user request), and the FPGA_DATA_READY any_pending formula is updated to the real counter-based implementation (credited to the user's own diagnosis) that fixed the last failing N=4 seed. Compiled clean (45 pages, 0 errors). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
136 lines
6.9 KiB
TeX
136 lines
6.9 KiB
TeX
\chapter{Host / graph-loader interface}
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\label{ch:host}
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\begin{fnwarn}[Scope of this chapter]
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V1's own host interface is a real, placed, physically-verified SPI Mode~0
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slave (ch.~7 of the V1 datasheet). V2's equivalent --- a node-registration
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bus into \code{neural\_multiprocessor.v} --- has, in this revision, been
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exercised exclusively from Verilator testbenches and unconstrained
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synthesis top-levels. This chapter describes the \textbf{logical}
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protocol only; no real host-side driver (SPI or otherwise) has been
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built or placed yet. See ch.~\ref{ch:roadmap}.
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\end{fnwarn}
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\section{Node registration protocol}
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A simple valid/ready producer interface, backpressure-safe: the loader
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holds \code{reg\_valid} and the node's own fields until \code{reg\_ready}
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is observed high on the same cycle, exactly like registering into any
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FIFO. \code{reg\_ready} for a given \code{reg\_node\_id} is asserted
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whenever that node's own table slot is \code{EMPTY} (\S\ref{ch:sched}).
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\begin{tabularx}{\textwidth}{L{3.2cm} C{1.6cm} Y}
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\toprule
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\rowh \thd{Field} & \thd{Width} & \thd{Meaning} \\
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\midrule
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\code{reg\_node\_id} & $\lceil\log_2\text{N\_NODES}\rceil$ & This node's own id --- doubles as its table slot index. \\
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\rowa \code{reg\_required} & $\lceil\log_2(\text{MAX\_DEPS}{+}1)\rceil$ & How many of \code{reg\_producer\_ids} are meaningful (0 $\Rightarrow$ immediately \code{READY}). \\
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\code{reg\_producer\_ids} & \code{MAX\_DEPS}$\times\lceil\log_2\text{N\_NODES}\rceil$ & Packed array of producer node ids this node depends on. \\
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\rowa \code{reg\_x\_base} & \code{ADDR\_WIDTH} & Base byte address of this node's activation vector. \\
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\code{reg\_w\_base} & \code{ADDR\_WIDTH} & Base byte address of this node's weight vector. \\
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\rowa \code{reg\_n\_tiles} & 16 & Number of P\_IN-wide tiles to accumulate. \\
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\code{reg\_result\_addr} & \code{ADDR\_WIDTH} & Byte address the computed INT8 result is written to. \\
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\bottomrule
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\end{tabularx}
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\begin{fnnote}[A node id is a real, finite resource]
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Because dispatched node table slots are never reclaimed
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(\S\ref{ch:sched}), a loader driving many independent jobs over a long
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session must use a fresh \code{reg\_node\_id} for each one, within
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\code{N\_NODES}. Reusing a value before the system has been reset will
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simply be refused (\code{reg\_ready} stays low for an occupied,
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non-\code{EMPTY} node id) --- it will not corrupt anything, but it will
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also not register.
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\end{fnnote}
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\section{Result readback}
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The computed INT8 result is written to \code{reg\_result\_addr} through
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the same real PSRAM chain every other memory access uses --- there is no
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separate result-readback port; the host/loader reads the result byte
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back from PSRAM directly, the same convention every V2 testbench in this
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project uses for verification.
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\section{What a real host driver would still need to add}
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\begin{itemize}
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\item Per-job \code{bias}/\code{activation} selection, currently
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hardcoded to \code{bias=0}/\code{ACT\_RELU} for every job
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(\S\ref{ch:datapath}).
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\end{itemize}
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\section{Addendum (2026-09-07) --- real physical transport and
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completion signal, both now closed}
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\label{sec:host-addendum}
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\begin{fnwarn}[Supersedes the two items removed from the list above]
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Both real gaps this chapter used to list are closed. This section is
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the current, real state.
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\end{fnwarn}
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\textbf{Physical transport}: \code{spi\_host\_bridge.v}, a real SPI
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Mode~0 slave, is the board's actual node-registration transport ---
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real ball assignments (\code{spi\_sclk}/\code{spi\_mosi}/
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\code{spi\_miso}/\code{spi\_cs\_n}) verified, real place\&route (see
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ch.~\ref{ch:hw}). WRITE\_JOB carries the full table from
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\S\ref{ch:host} above as an 18-byte payload (grew from 15 after the
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64MB memory upgrade widened every address field from 3 to 4 bytes ---
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\code{decisions.log} DEC-0039).
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\textbf{Completion notification}: \code{FPGA\_DATA\_READY}, a real
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output pin (ball \code{G3}, bank~7), closes the exact gap this
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chapter used to flag. It is a system-idle detector, not a per-job
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pulse --- deliberately, since ``the whole graph has an answer'' and
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``one neuron finished'' are different questions and only the former is
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useful to a host waiting on a result:
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\[
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\text{sys\_busy} = \big(\textstyle\bigvee \text{job\_active}\big)
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\;\lor\; \lnot\text{queue\_empty} \;\lor\; \text{any\_pending}
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\]
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where \code{job\_active} is per-slot (already real, \S\ref{ch:sched}),
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\code{queue\_empty} is \code{neural\_director.v}'s own dispatch-queue
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occupancy, and \code{any\_pending} tracks whether any node is
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currently registered but not yet dispatched (\code{WAITING} or
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\code{READY} --- \code{DISPATCHED} nodes are tracked by the two
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signals above instead, not here).
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\begin{fnwarn}[Updated 2026-09-07 --- \code{any\_pending} implementation changed]
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The first real implementation computed \code{any\_pending} as a
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combinational OR-reduce over \code{dependency\_manager}'s own
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\code{node\_state[0:N\_NODES-1]} array every cycle. A real 8-seed
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\code{nextpnr-ecp5} P\&R sweep later showed this adding genuine
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fan-out onto \code{node\_state} --- a signal that also sits on this
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project's own worst real critical path
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(\code{neural\_director.job\_out\_slot} $\to$
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\code{dependency\_manager.node\_resolved}/\code{node\_state}), costing
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real Fmax margin (traced to a real 62.47\,MHz failing seed at
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N\_SLOTS=4 \S64\,MHz --- see ch.~\ref{ch:hw} \S\ref{sec:clock-closure-current}).
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Replaced (the user's own suggestion) with a synchronous up/down
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counter: \code{pending\_count} increments on a node's own registration
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acceptance (\code{reg\_valid\&\®\_ready}) and decrements on its own
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dispatch acceptance (\code{ready\_valid\&\&ready\_ready}); \code{any\_pending
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= (pending\_count != 0)}. Mathematically identical to the original
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OR-reduce (nodes are never reclaimed mid-run, ch.~\ref{ch:sched}), but
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reads one small registered counter instead of scanning a 16-wide array
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every cycle --- zero added fan-out on the congested signal. Recovered
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the last failing N\_SLOTS=4 seed (62.47 $\to$ 64.55\,MHz), closing
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8/8. See \code{decisions.log} DEC-0042.
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\end{fnwarn}
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\code{FPGA\_DATA\_READY} is a sticky
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register: set on the \code{sys\_busy} $1\to0$ edge, cleared the
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instant \code{sys\_busy} goes high again --- self-clearing, no host
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acknowledgement command needed.
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\begin{fnnote}[Real, disclosed assumption]
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This is correct only if the host finishes registering every node of a
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graph before the first one completes. Realistic for this
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architecture's own real timing (SPI registration: microseconds;
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per-neuron compute: $\sim$195 real measured cycles, \S\ref{ch:impl2})
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but not proven for every conceivable host registration pattern --- a
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host that deliberately staggers registration across a long enough gap
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could observe a premature \code{FPGA\_DATA\_READY} pulse after only
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the first node completes.
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\end{fnnote}
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Bit-exact regression re-verified with an explicit assertion on this
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signal (N\_SLOTS=4 and 8, both PASS, see \code{decisions.log}
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DEC-0041) and a real \code{nextpnr-ecp5} placement check (0 errors,
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\code{data\_ready} placed at \code{G3}).
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