Files

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micheleandClaude Sonnet 5 e7f9b9f719 docs: add real BOM, flag FPGA grade discrepancy (8BG381I vs 8BG381C)

Real KiCad-exported BOM added to the hardware chapter, cross-checked
against every component value this chapter already specifies -- most
match exactly (R1/R2 feedback divider, L1/L2, ferrite part number, all
three real ICs). One real discrepancy found: U2 is captured as
LFE5U-45F-8BG381I (industrial grade) while every other reference in
this project uses the C (commercial) grade part -- flagged, not
resolved, needs explicit confirmation.

Also resolves three earlier open items from the schematic review:
R3=499k confirms TLV62568's EN is populated; R5-R12 being 8 discrete
0402 resistors (not a multi-resistor array) confirms the JTAG
pull-up/down polarity concern doesn't apply; U5 confirms the
previously-missing 16MHz oscillator is now present.

Compiled clean (47 pages, 0 errors).

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

2026-09-07 19:36:51 +02:00

chapters

docs: bring datasheet/ into the main repo under hardware/v2/docs

2026-09-07 05:09:14 +02:00

docs: bring datasheet/ into the main repo under hardware/v2/docs

2026-09-07 05:09:14 +02:00

v2-en

docs: add real BOM, flag FPGA grade discrepancy (8BG381I vs 8BG381C)

2026-09-07 19:36:51 +02:00

FPGA-Neural-Datasheet.pdf

docs: bring datasheet/ into the main repo under hardware/v2/docs

2026-09-07 05:09:14 +02:00

FPGA-Neural-Datasheet.tex

docs: bring datasheet/ into the main repo under hardware/v2/docs

2026-09-07 05:09:14 +02:00

preamble.tex

docs: bring datasheet/ into the main repo under hardware/v2/docs

2026-09-07 05:09:14 +02:00

README.md

docs: bring datasheet/ into the main repo under hardware/v2/docs

2026-09-07 05:09:14 +02:00

README.md

FPGA-Neural — Datasheet

Datasheet tecnico multicapitolo dell'engine FPGA-Neural, in italiano e inglese. Ricostruito a partire dal codice RTL, dalla documentazione e dai benchmark presenti nella repository (revisione A1, settembre 2026).

Struttura

docs/datasheet/
├── FPGA-Neural-Datasheet.pdf        ← PDF italiano (36 pagine)
├── FPGA-Neural-Datasheet.tex        ← sorgente principale (IT)
├── preamble.tex                     ← stili, palette, box, TikZ
├── chapters/                        ← 14 capitoli (IT)
└── en/
    ├── FPGA-Neural-Datasheet-EN.pdf ← PDF inglese (36 pagine)
    ├── FPGA-Neural-Datasheet-EN.tex ← sorgente principale (EN)
    ├── preamble.tex                 ← stili (EN)
    └── chapters/                    ← 14 capitoli (EN)

Compilazione

Serve una distribuzione LaTeX con pgfplots, tikz-timing, tcolorbox, ltablex, listings, babel.

# Italiano
cd docs/datasheet
pdflatex FPGA-Neural-Datasheet.tex
pdflatex FPGA-Neural-Datasheet.tex   # 2ª passata per indice e riferimenti

# Inglese
cd docs/datasheet/en
pdflatex FPGA-Neural-Datasheet-EN.tex
pdflatex FPGA-Neural-Datasheet-EN.tex

Nota sul pinout

Il capitolo Progetto hardware e mappa dei segnali riporta l'analisi completa segnale-per-segnale del top-level spi_neuron_top, con la colonna Ball compilata con assegnazioni CABGA381 reali (53 segnali, .lpf reale in synth/) e verificata da un place&route reale (nextpnr-ecp5, 0 errori di vincolo, Program finished normally) — non più auto-piazzate.