micheleandClaude Sonnet 5
0e73eb4726
Was a separate, untracked directory (DataSheet/) outside the repo. Renamed to lowercase and moved in as hardware/v2/docs/datasheet/, with its own .gitignore for LaTeX build byproducts (compiled PDFs stay tracked, .aux/.log/.toc/etc do not). Now versioned and shares this repo's own remote instead of living untracked on disk. Content: IT+EN LaTeX chapter sources, reference manufacturer PDFs, and compiled datasheet PDFs including the 2026-09-07 SDRAM upgrade addendum (AS4C32M16SB-7BIN part/pinout/timing) in the v2-en chapters. Note: hardware/v2/docs/DatasheetLatex/ (and the v1 sibling) is a separate, already-tracked, differently-structured LaTeX document that predates this move -- left untouched, not merged, since its chapter set and content differ and merging was not requested. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
65 lines
4.0 KiB
TeX
65 lines
4.0 KiB
TeX
\chapter{Roadmap and development status}
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\label{ch:roadmap}
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\section{Development phases}
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\begin{tabularx}{\textwidth}{C{1.2cm} L{4.6cm} C{1.8cm} Y}
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\toprule
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\rowh \thd{Phase} & \thd{Title} & \thd{Status} & \thd{Content} \\
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\midrule
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1 & Parametric layer & \OK & inputs/neurons/parallelism, accumulation, bias, ReLU; test 32$\times$4/P=8. \\
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\rowa 2 & Parameter sweep & \OK & multiple configurations incl. non-multiple and degenerate; elaboration guard added. \\
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3 & Memory architecture & \OK & \code{neuron\_memory} single/multi-neuron, real PSRAM tested; multi-layer buffers $\to$ Phase~5. \\
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\rowa 4 & SPI interface & \OK & \code{spi\_slave}+\code{spi\_engine}, 17 opcodes incl. flash subsystem, Fmax checked at full-system level. \\
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5 & Multi-layer network & \OK$^\dagger$ & \code{layer\_sequencer}, configurable activations, runtime width; real toolchain checked. \\
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\rowa 6 & Host software & planned & Linux and ESP32 drivers on the same protocol. \\
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7 & Optimization & in progress & timing closure done (55$\to$75~MHz); PSRAM page-mode done (gather bandwidth +42\%); $x$/$w$ block RAM remains. \\
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\rowa 8 & Hardware training (opt.) & future & backprop, gradients, weight update. \\
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9 & Flash subsystem (F1-F7) & \OK & dedicated SPI master, flash$\leftrightarrow$PSRAM copy engine, 16-slot catalog with CRC32, fully independent 4-wire SPI bus (F7), 8 opcodes (\op{0x40}--\op{0x47}, ch.~\ref{ch:spi} §\ref{sec:flashspi}); real synthesis 0 errors. \\
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\bottomrule
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\end{tabularx}
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\begin{center}\footnotesize\itshape\color{fnGrey}
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$\dagger$ RTL, unit tests and end-to-end over simulated SPI complete; timing closure done:
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75.30~MHz (P2) / 60.26~MHz (P8) at the time of Phase~5, bit-exact across the whole
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regression; Fmax of the full system after Phase~9 (incl. independent flash subsystem):
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\textbf{67.91~MHz} (ch.~\ref{ch:impl}).\end{center}
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\section{Component status}
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\begin{tabularx}{\textwidth}{Y C{4.2cm}}
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\toprule
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\rowh \thd{Component} & \thd{Status} \\
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\midrule
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Parametric neural layer & \OK{} working \\
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\rowa Parametric inputs/neurons/parallelism & \OK \\
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Accumulation, bias, ReLU & \OK \\
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\rowa 32$\times$4 / P=8 validation & \OK \\
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Dedicated RAM (interface + controller + INT8 access) & \OK{} tested on real PSRAM \\
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\rowa SPI interface (17 opcodes incl. RUN\_NETWORK + flash) & \OK{} Fmax at full-system level \\
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Dual SPI & future \\
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\rowa Multi-layer engine & \OK{} timing closure 75.30~MHz (P2) at the time of Phase~5 \\
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Configurable activations (ACT\_NONE/ACT\_RELU) & \OK \\
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\rowa Runtime network width (one bitstream, any topology) & \OK{} measured savings \\
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Type \#2 graph network (act\_buffer, graph\_engine, netasm) & \OK{} RTL + tests + synthesis \\
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\rowa CABGA381 pinout (real \code{.lpf}, 57 signals incl. flash) & \OK{} place\&route-verified, 0 errors \\
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PSRAM page-mode (G7) & \OK{} done (37.53 cycles/edge, bandwidth +42\%) \\
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\rowa Flash subsystem (SPI master, copy engine, CRC32 catalog, independent bus F7) & \OK{} real synthesis 0 errors, Fmax 67.91~MHz \\
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Real bitstream (\code{ecppack}, P2/P8) & \OK{} 0 errors, part LFE5U-45F-8CABGA381 \\
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\rowa Linux / ESP32 host driver & planned \\
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Hardware training & future \\
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\bottomrule
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\end{tabularx}
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\section{Architectural principle (summary)}
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\begin{fnspec}[Foundation of the project]
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The FPGA implements the neural machine and owns its own RAM; the host configures and uses
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the machine. A build fixes the \emph{ceiling} (max layers, max width, PARALLEL); the host
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configures the \emph{actual} network --- number of layers, per-layer width, per-layer
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activation, trained parameters --- entirely at runtime, over SPI, into the FPGA's local
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memory. A single bitstream serves any topology up to that ceiling.
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\end{fnspec}
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\section{Long-term vision}
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The final goal is a reusable hardware block integrable into different future projects:
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the host platform can change (Linux, ESP32, MCU, PC) without changing the fundamental
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architecture of the engine. The FPGA becomes a dedicated neural computation peripheral,
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optimized for the topology required by each application.
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