micheleandClaude Sonnet 5
0e73eb4726
Was a separate, untracked directory (DataSheet/) outside the repo. Renamed to lowercase and moved in as hardware/v2/docs/datasheet/, with its own .gitignore for LaTeX build byproducts (compiled PDFs stay tracked, .aux/.log/.toc/etc do not). Now versioned and shares this repo's own remote instead of living untracked on disk. Content: IT+EN LaTeX chapter sources, reference manufacturer PDFs, and compiled datasheet PDFs including the 2026-09-07 SDRAM upgrade addendum (AS4C32M16SB-7BIN part/pinout/timing) in the v2-en chapters. Note: hardware/v2/docs/DatasheetLatex/ (and the v1 sibling) is a separate, already-tracked, differently-structured LaTeX document that predates this move -- left untouched, not merged, since its chapter set and content differ and merging was not requested. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
98 lines
4.7 KiB
TeX
98 lines
4.7 KiB
TeX
\chapter[Moduli e toolchain]{Moduli, porte e toolchain}
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\label{ch:appmod}
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\section{Elenco dei moduli RTL}
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\begin{tabularx}{\textwidth}{L{3.4cm} C{2.0cm} Y}
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\toprule
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\rowh \thd{File} & \thd{Tipo} & \thd{Ruolo} \\
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\midrule
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\code{rtl/mac\_unit.v} & combinatorio & prodotto-accumulatore singolo \\
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\rowa \code{rtl/mac8.v} & combinatorio & MAC parallelo + adder tree bilanciato \\
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\code{rtl/neuron\_parallel.v} & FSM & neurone: gruppi, bias, attivazione, saturazione \\
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\rowa \code{rtl/layer.v} & strutturale & N\_NEURONS neuroni in parallelo \\
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\code{rtl/neuron\_memory.v} & FSM & ponte memoria/neurone, loop neuroni \\
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\rowa \code{rtl/layer\_sequencer.v} & FSM & sequenza multi-layer, ping-pong \\
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\code{rtl/int8\_memory\_access.v} & FSM & conversione byte $\leftrightarrow$ word \\
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\rowa \code{rtl/memory\_interface.v} & FSM & handshake req/ready \\
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\code{rtl/psram\_controller.v} & FSM & bus fisico PSRAM async, page mode 70/20~ns \\
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\rowa \code{rtl/mem\_arbiter.v} & arbitro & 3 porte, priorità B$>$C$>$A \\
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\code{rtl/spi\_slave.v} & FSM & layer fisico SPI Mode 0 + CDC \\
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\rowa \code{rtl/spi\_engine.v} & FSM & opcode + banco registri \\
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\code{rtl/act\_buffer.v} & block RAM & buffer di attivazione DP16KD (Tipo \#2) \\
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\rowa \code{rtl/graph\_engine.v} & FSM & motore rete a grafo (Tipo \#2) \\
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\code{rtl/spi\_neuron\_top.v} & top & integrazione completa \\
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\rowa \code{rtl/memory\_model.v} & modello & RAM comportamentale (sim) \\
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\bottomrule
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\end{tabularx}
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\section{Porte del top-level \texttt{spi\_neuron\_top}}
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Vedere la tabella segnale-per-segnale completa nel cap.~\ref{ch:hw}. In sintesi: clock
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e reset (\code{clk}, \code{rst}); SPI applicativo (\code{sclk}, \code{mosi},
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\code{miso}, \code{cs\_n}); bus PSRAM (\code{psram\_a[22:0]}, \code{psram\_dq[15:0]},
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\code{psram\_ce\_n/oe\_n/we\_n/lb\_n/ub\_n/zz\_n}).
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\section{Toolchain}
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\begin{tabularx}{\textwidth}{L{3.6cm} L{3.4cm} Y}
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\toprule
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\rowh \thd{Strumento} & \thd{Versione} & \thd{Uso} \\
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\midrule
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Yosys & 0.68+post & sintesi RTL $\to$ netlist JSON, mapping ECP5 \\
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\rowa nextpnr-ecp5 & 0.11.1-19-g8dbcee5 & placement, routing, timing \\
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Project Trellis & install & \code{ecppack}/\code{ecppll}/\code{ecpbram} \\
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\rowa Icarus Verilog & \code{-g2012} & simulazione funzionale \\
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\bottomrule
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\end{tabularx}
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\subsection{Parametri nextpnr principali}
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\begin{lstlisting}[language=,basicstyle=\ttfamily\scriptsize]
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--45k seleziona LFE5U-45F
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--package CABGA381 package
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--speed 8 speed grade -8
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--json <netlist> netlist da Yosys
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--lpf <vincoli> vincoli di pin (attualmente vuoti)
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--lpf-allow-unconstrained permette I/O non vincolate (benchmark)
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--freq 80 timing target 80 MHz
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\end{lstlisting}
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\subsection{Esempio di simulazione}
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\begin{lstlisting}[language=,basicstyle=\ttfamily\scriptsize]
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iverilog -g2012 -Ptb.PARALLEL=16 -o sim/parametric_256x4_p16 \
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sim/parametric_tb.v rtl/mac_unit.v rtl/mac8.v \
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rtl/neuron_parallel.v rtl/layer.v
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vvp sim/parametric_256x4_p16
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\end{lstlisting}
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\section{Testbench principali}
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\begin{tabularx}{\textwidth}{L{5.4cm} Y}
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\toprule
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\rowh \thd{Testbench} & \thd{Copertura} \\
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\midrule
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\code{parametric\_tb.v} & datapath 256$\times$4, casi accumulo/bias/ReLU/saturazione \\
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\rowa \code{parameter\_sweep\_tb.v} & sweep configurazioni valide \\
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\code{neuron\_parallel\_tb.v} & attivazioni, larghezza runtime (T7) \\
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\rowa \code{neuron\_memory\_tb.v} / \code{\_multi\_tb.v} & integrazione memoria mono/multi-neurone, PSRAM reale (T5) \\
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\code{psram\_controller\_tb.v} & controller PSRAM \\
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\rowa \code{psram\_page\_mode\_tb.v} & burst di pagina, attraversamento pagina, chiusura su WRITE/timeout $t_{CEM}$, cambi di byte-enable (§~5.5) \\
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\code{spi\_slave\_tb.v} & layer fisico SPI (4 test) \\
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\rowa \code{spi\_engine\_tb.v} & opcode, registri (10+ test) \\
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\code{spi\_neuron\_top\_tb.v} & end-to-end, PSRAM reale su SPI simulato \\
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\rowa \code{spi\_neuron\_top\_runnetwork\_tb.v} & RUN\_NETWORK 2 layer end-to-end \\
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\code{layer\_sequencer\_tb.v} & sequenza 2 layer, ping-pong, copia byte-exact \\
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\bottomrule
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\end{tabularx}
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\vfill
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\begin{center}
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\begin{tikzpicture}
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\node[draw=fnRule,rounded corners=3pt,inner sep=8pt,fill=fnLight,text width=15.5cm]{
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\footnotesize\color{fnGrey}
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Questo datasheet è generato a partire dal codice RTL, dalla documentazione e dai
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benchmark presenti nella repository \texttt{github.com/manvalan/FPGA-Neural} allo stato
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del \datasheetdate. I valori di Fmax, utilizzo risorse e throughput sono quelli
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riportati nelle misure della repository (\texttt{.lpf} reale già assegnato e
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verificato da place\&route, cap.~\ref{ch:hw}) e vanno riverificati ad ogni
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variazione sostanziale dell'RTL o della chiusura del timing di Fase~7, tuttora in
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corso (cap.~\ref{ch:roadmap}).};
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\end{tikzpicture}
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\end{center}
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