micheleandClaude Sonnet 5
0e73eb4726
Was a separate, untracked directory (DataSheet/) outside the repo. Renamed to lowercase and moved in as hardware/v2/docs/datasheet/, with its own .gitignore for LaTeX build byproducts (compiled PDFs stay tracked, .aux/.log/.toc/etc do not). Now versioned and shares this repo's own remote instead of living untracked on disk. Content: IT+EN LaTeX chapter sources, reference manufacturer PDFs, and compiled datasheet PDFs including the 2026-09-07 SDRAM upgrade addendum (AS4C32M16SB-7BIN part/pinout/timing) in the v2-en chapters. Note: hardware/v2/docs/DatasheetLatex/ (and the v1 sibling) is a separate, already-tracked, differently-structured LaTeX document that predates this move -- left untouched, not merged, since its chapter set and content differ and merging was not requested. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
105 lines
5.6 KiB
TeX
105 lines
5.6 KiB
TeX
\thispagestyle{plain}
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\noindent
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\begin{tikzpicture}
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\node[fill=fnDark,text=white,rounded corners=2pt,inner sep=6pt,
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minimum width=\textwidth,anchor=west]
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{\large\bfseries Sunto del pinout --- collegamento pin per pin};
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\end{tikzpicture}
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\vspace{6pt}
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\noindent
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{\footnotesize
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Tabella di riferimento rapido: i \textbf{57 segnali reali} del top-level
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\code{spi\_neuron\_top}, ciascuno con la propria ball \code{CABGA381}
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individuale (\textbf{non} un intervallo di bus) --- dati reali dal database
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di dispositivo di Project~Trellis (\code{iodb.json}), \textbf{verificati da
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un place\&route \code{nextpnr-ecp5} completo a 0 errori} (non un pinout
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pianificato). Descrizione completa, razionale di collocazione per banco e
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schema di collegamento pin-per-pin verso la PSRAM ISSI: cap.~\ref{ch:hw}.
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}
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\vspace{4pt}
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\noindent
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\renewcommand{\arraystretch}{1.08}
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\begin{tabularx}{\textwidth}{L{2.7cm} C{1.0cm} C{1.0cm} C{0.9cm} Y}
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\toprule
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\rowh \thd{Segnale} & \thd{Ball} & \thd{Banco} & \thd{Dir} & \thd{Pin corrispondente / funzione} \\
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\midrule
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\multicolumn{5}{l}{\textit{\color{fnDark}Clock e reset}}\\
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\code{clk} & H5 & 7 & IN & Clock di sistema, pad \code{GR\_PCLK7\_0} (clock globale dedicato). \\
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\rowa \code{rst} & B4 & 7 & IN & Reset globale sincrono, attivo alto. \\
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\multicolumn{5}{l}{\textit{\color{fnDark}SPI applicativo (host $\leftrightarrow$ FPGA, Mode~0)}}\\
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\code{sclk} & B5 & 7 & IN & SPI clock (CPOL=0, CPHA=0). \\
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\rowa \code{mosi} & C5 & 7 & IN & Master-Out Slave-In. \\
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\code{miso} & A3 & 7 & OUT & Master-In Slave-Out. \\
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\rowa \code{cs\_n} & B3 & 7 & IN & Chip-select, attivo basso. \\
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\multicolumn{5}{l}{\textit{\color{fnDark}Attenzione host (attivi bassi, di livello)}}\\
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\code{data\_ready\_n} & C3 & 7 & OUT & Basso finché un risultato attende lettura. \\
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\rowa \code{irq\_n} & C4 & 7 & OUT & Basso se il guard load-time del grafo è scattato. \\
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\multicolumn{5}{l}{\textit{\color{fnDark}Flash subsystem --- SPI verso W25Q128JV (boot/persistenza)}}\\
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\code{flash\_sclk} & E3 & 7 & OUT & SPI clock verso la flash --- GPIO ordinario, indipendente (Fase F7, cap.~\ref{ch:hw}). \\
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\rowa \code{flash\_mosi} & D3 & 7 & OUT & Master-Out Slave-In verso la flash NOR onboard. \\
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\code{flash\_miso} & D5 & 7 & IN & Master-In Slave-Out dalla flash. \\
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\rowa \code{flash\_cs\_n} & E4 & 7 & OUT & Chip-select flash, attivo basso. \\
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\multicolumn{5}{l}{\textit{\color{fnDark}Bus indirizzi PSRAM --- \code{psram\_a[21:0]} (22 linee reali)}}\\
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\code{psram\_a[0]} & E16 & 2 & OUT & PSRAM A0 \\
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\rowa \code{psram\_a[1]} & F16 & 2 & OUT & PSRAM A1 \\
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\code{psram\_a[2]} & D18 & 2 & OUT & PSRAM A2 \\
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\rowa \code{psram\_a[3]} & E17 & 2 & OUT & PSRAM A3 \\
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\code{psram\_a[4]} & E18 & 2 & OUT & PSRAM A4 \\
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\rowa \code{psram\_a[5]} & F18 & 2 & OUT & PSRAM A5 \\
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\code{psram\_a[6]} & F17 & 2 & OUT & PSRAM A6 \\
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\rowa \code{psram\_a[7]} & G16 & 2 & OUT & PSRAM A7 \\
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\code{psram\_a[8]} & G18 & 2 & OUT & PSRAM A8 \\
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\rowa \code{psram\_a[9]} & H16 & 2 & OUT & PSRAM A9 \\
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\code{psram\_a[10]} & H17 & 2 & OUT & PSRAM A10 \\
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\rowa \code{psram\_a[11]} & H18 & 2 & OUT & PSRAM A11 \\
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\code{psram\_a[12]} & J16 & 2 & OUT & PSRAM A12 \\
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\rowa \code{psram\_a[13]} & J17 & 2 & OUT & PSRAM A13 \\
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\code{psram\_a[14]} & C20 & 2 & OUT & PSRAM A14 \\
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\rowa \code{psram\_a[15]} & D19 & 2 & OUT & PSRAM A15 \\
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\code{psram\_a[16]} & E19 & 2 & OUT & PSRAM A16 \\
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\rowa \code{psram\_a[17]} & E20 & 2 & OUT & PSRAM A17 \\
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\code{psram\_a[18]} & F19 & 2 & OUT & PSRAM A18 \\
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\rowa \code{psram\_a[19]} & F20 & 2 & OUT & PSRAM A19 \\
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\code{psram\_a[20]} & G20 & 2 & OUT & PSRAM A20 \\
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\rowa \code{psram\_a[21]} & H20 & 2 & OUT & PSRAM A21 \\
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\code{psram\_a[22]} & P18 & 3 & OUT & Sempre 0 (shift byte$\to$word) --- NC su scheda. \\
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\multicolumn{5}{l}{\textit{\color{fnDark}Bus dati PSRAM --- \code{psram\_dq[15:0]} (bidirezionale)}}\\
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\rowa \code{psram\_dq[0]} & K18 & 2 & IO & PSRAM DQ0 \\
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\code{psram\_dq[1]} & C18 & 2 & IO & PSRAM DQ1 \\
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\rowa \code{psram\_dq[2]} & D17 & 2 & IO & PSRAM DQ2 \\
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\code{psram\_dq[3]} & D20 & 2 & IO & PSRAM DQ3 \\
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\rowa \code{psram\_dq[4]} & G19 & 2 & IO & PSRAM DQ4 \\
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\code{psram\_dq[5]} & J18 & 2 & IO & PSRAM DQ5 \\
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\rowa \code{psram\_dq[6]} & J19 & 2 & IO & PSRAM DQ6 \\
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\code{psram\_dq[7]} & J20 & 2 & IO & PSRAM DQ7 \\
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\rowa \code{psram\_dq[8]} & K19 & 2 & IO & PSRAM DQ8 \\
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\code{psram\_dq[9]} & K20 & 2 & IO & PSRAM DQ9 \\
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\rowa \code{psram\_dq[10]} & L17 & 3 & IO & PSRAM DQ10 \\
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\code{psram\_dq[11]} & M18 & 3 & IO & PSRAM DQ11 \\
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\rowa \code{psram\_dq[12]} & M17 & 3 & IO & PSRAM DQ12 \\
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\code{psram\_dq[13]} & N16 & 3 & IO & PSRAM DQ13 \\
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\rowa \code{psram\_dq[14]} & N18 & 3 & IO & PSRAM DQ14 \\
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\code{psram\_dq[15]} & P17 & 3 & IO & PSRAM DQ15 \\
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\multicolumn{5}{l}{\textit{\color{fnDark}Controllo PSRAM}}\\
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\rowa \code{psram\_ce\_n} & N17 & 3 & OUT & PSRAM CE\# --- chip enable, attivo basso. \\
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\code{psram\_oe\_n} & R16 & 3 & OUT & PSRAM OE\# --- output enable (lettura). \\
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\rowa \code{psram\_we\_n} & R17 & 3 & OUT & PSRAM WE\# --- write enable (scrittura). \\
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\code{psram\_lb\_n} & T16 & 3 & OUT & PSRAM LB\# --- lower-byte enable (DQ[7:0]). \\
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\rowa \code{psram\_ub\_n} & N19 & 3 & OUT & PSRAM UB\# --- upper-byte enable (DQ[15:8]). \\
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\code{psram\_zz\_n} & N20 & 3 & OUT & PSRAM ZZ\# --- sleep/snooze (alto in funzionamento). \\
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\bottomrule
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\end{tabularx}
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\renewcommand{\arraystretch}{1.25}
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\vspace{4pt}
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\noindent
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{\footnotesize\color{fnGrey}
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Standard I/O: LVCMOS33 su tutti i 57 segnali. Ball di JTAG e config-SPI di
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boot (pin dedicati a funzione fissa, senza porta RTL) non compaiono in
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questa tabella --- vedi cap.~\ref{ch:hw} §``Configurazione e
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programmazione''. Sorgente: \code{synth/ecp5/spi\_neuron\_top.lpf},
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generato da \code{tools/pinout/gen\_lpf.py} contro
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\code{iodb.json} di Project~Trellis.\par}
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