micheleandClaude Sonnet 5
0e73eb4726
Was a separate, untracked directory (DataSheet/) outside the repo. Renamed to lowercase and moved in as hardware/v2/docs/datasheet/, with its own .gitignore for LaTeX build byproducts (compiled PDFs stay tracked, .aux/.log/.toc/etc do not). Now versioned and shares this repo's own remote instead of living untracked on disk. Content: IT+EN LaTeX chapter sources, reference manufacturer PDFs, and compiled datasheet PDFs including the 2026-09-07 SDRAM upgrade addendum (AS4C32M16SB-7BIN part/pinout/timing) in the v2-en chapters. Note: hardware/v2/docs/DatasheetLatex/ (and the v1 sibling) is a separate, already-tracked, differently-structured LaTeX document that predates this move -- left untouched, not merged, since its chapter set and content differ and merging was not requested. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
89 lines
4.3 KiB
TeX
89 lines
4.3 KiB
TeX
\chapter{Parameters and configurability}
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\label{ch:param}
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\section{Build parameters (synthesis-time)}
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The hardware architecture is fixed at synthesis through the following Verilog
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parameters. They determine the datapath contained in the bitstream and its capacity
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\emph{ceiling}.
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\begin{tabularx}{\textwidth}{L{3.0cm} C{1.8cm} Y}
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\toprule
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\rowh \thd{Parameter} & \thd{Default} & \thd{Meaning} \\
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\midrule
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\code{DATA\_WIDTH} & 8 & Data width (INT8). \\
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\rowa \code{ACC\_WIDTH} & 32 & Accumulator width (INT32). \\
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\code{N\_INPUTS} & 32 / 256 & Maximum number of inputs per neuron (benchmark baseline: 256). \\
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\rowa \code{N\_NEURONS} & 1 / 4 & Maximum number of neurons per layer. \\
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\code{PARALLEL} & 8 & Simultaneous hardware MACs per neuron; must divide \code{N\_INPUTS} and should be a power of two. \\
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\rowa \code{N\_LAYERS} & 4 & Maximum number of layers chainable by \code{layer\_sequencer}. \\
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\code{ADDR\_WIDTH} & 23 & Byte-address width (8~MB). \\
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\rowa \code{MEM\_DATA\_WIDTH} & 16 & Width of the physical PSRAM data bus. \\
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\code{CLK\_FREQ\_MHZ} & 80 & Frequency used in the PSRAM timing formulas (must be aligned to the real oscillator). \\
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\bottomrule
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\end{tabularx}
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\begin{fnwarn}[\texttt{N\_INPUTS} \% \texttt{PARALLEL} constraint]
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\code{PARALLEL} must divide \code{N\_INPUTS} exactly, otherwise the elaboration guard
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fires (§\ref{ch:datapath}). The same constraint applies at runtime to
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\code{n\_inputs\_real}.
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\end{fnwarn}
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\section{Runtime network width}
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A single bitstream serves any topology \emph{up to} the build maximum. The actual width
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of each execution is a separate value, set by the host:
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\begin{itemize}
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\item \code{n\_inputs\_real} --- inputs actually used in this execution (must be a
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multiple of \code{PARALLEL});
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\item \code{n\_neurons\_real} --- neurons actually computed in this execution.
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\end{itemize}
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Both default to the build maximum, so any caller that leaves them unconnected processes
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the full width as before the ports were introduced.
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\begin{fnnote}[Real early termination]
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This is not mere address bookkeeping: the two values directly bound the hardware loops
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(X/W reads of \code{neuron\_memory}, MAC group count of \code{neuron\_parallel} and the
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length of the ping-pong copy for \code{RUN\_NETWORK}). A narrower layer actually
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\emph{computes} and \emph{copies} faster and does not require zero-padding of the RAM
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for the unused tail: data beyond \code{n\_inputs\_real}/\code{n\_neurons\_real} is never
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read.
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\end{fnnote}
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This lets a network taper within a single chained execution, for example
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$256\to64\to16\to4$, with each layer declaring its own actual width in the descriptor
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table (ch.~\ref{ch:seq}).
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\subsection{Measured savings}
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Early termination was measured end-to-end:
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\begin{tabularx}{\textwidth}{L{5.5cm} C{3.0cm} Y}
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\toprule
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\rowh \thd{Test} & \thd{Cycles} & \thd{Comparison} \\
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\midrule
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\code{neuron\_parallel\_tb.v} (T7) & 3 vs 6 & reduced vs full, with ``garbage'' data in the skipped lanes (proof that they are not read). \\
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\rowa \code{neuron\_memory\_tb.v} (T5) & 209 vs 788 & 8-of-32 vs full 32, through the real PSRAM stack. \\
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\bottomrule
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\end{tabularx}
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\section{Characterized configurations}
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Some combinations validated in simulation and/or synthesis:
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\begin{tabularx}{\textwidth}{C{2.0cm} C{2.0cm} C{2.0cm} Y}
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\toprule
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\rowh \thd{N\_INPUTS} & \thd{N\_NEURONS} & \thd{PARALLEL} & \thd{Notes} \\
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\midrule
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32 & 4 & 8 & First functional parametric test (Phase~1). \\
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\rowa 256 & 4 & 2/4/8/16 & Datapath benchmark sweep (Phase~7). \\
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32 & 1..3 & 8 & Single/multi-neuron memory integration (Phase~3). \\
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\rowa 4 & 4 & 2 & End-to-end 2-layer \code{RUN\_NETWORK} test over real SPI. \\
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\bottomrule
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\end{tabularx}
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\section{Build versus runtime summary}
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\begin{center}
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\begin{tikzpicture}[font=\footnotesize,node distance=6mm]
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\node[fnblockD,minimum width=54mm,minimum height=15mm](b){\textbf{BUILD (synthesis)}\\[2pt]
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{\scriptsize N\_INPUTS, N\_NEURONS, N\_LAYERS,}\\{\scriptsize PARALLEL, DATA\_WIDTH, ACC\_WIDTH}\\{\scriptsize $\Rightarrow$ machine ceiling}};
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\node[fnblockT,right=16mm of b,minimum width=54mm,minimum height=15mm](r){\textbf{RUNTIME (host, SPI)}\\[2pt]
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{\scriptsize n\_inputs\_real, n\_neurons\_real,}\\{\scriptsize activation, num\_layers, weights/bias}\\{\scriptsize $\Rightarrow$ actual network}};
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\draw[fnbus] (b) -- node[fnlbl,above]{$\le$} (r);
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\end{tikzpicture}
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\end{center}
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