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micheleandClaude Sonnet 5 85d473a79b docs: embed real KiCad schematic export in V2 datasheet, verify BOM from source

Exported the schematic (kicad-cli sch export pdf) and BOM (kicad-cli sch
export bom) directly from the real KiCad source instead of relying on
pasted screenshots/CSVs, then updated ch.10 accordingly:

- New "Real KiCad schematic capture" section embeds the two live sheets
  (FPGA, UnusedBank) as vector figures pulled straight from the project
  file, plus a note on the three sheet files not reachable from the
  root hierarchy.
- Boot-flash net-name mismatch finding confirmed resolved: FPGA_SPI_*
  labels now match exactly on both the flash chip and the ECP5's
  dedicated MSPI pins.
- FPGA grade fix (8BG381I -> 8BG381C) now verified directly in the
  source file's Value field, not just as a stated intent. Real package
  geometry added: 0.8mm pitch, 20x20 array, 17x17x1.76mm body.
- New minor finding: U2's footprint library folder is still named
  ..._8BG381I even though the Value field is corrected -- not
  board-affecting (identical physical footprint across grades), but
  flagged for a future rename.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

2026-09-07 20:03:57 +02:00

chapters

docs: bring datasheet/ into the main repo under hardware/v2/docs

2026-09-07 05:09:14 +02:00

docs: bring datasheet/ into the main repo under hardware/v2/docs

2026-09-07 05:09:14 +02:00

v2-en

docs: embed real KiCad schematic export in V2 datasheet, verify BOM from source

2026-09-07 20:03:57 +02:00

FPGA-Neural-Datasheet.pdf

docs: bring datasheet/ into the main repo under hardware/v2/docs

2026-09-07 05:09:14 +02:00

FPGA-Neural-Datasheet.tex

docs: bring datasheet/ into the main repo under hardware/v2/docs

2026-09-07 05:09:14 +02:00

preamble.tex

docs: bring datasheet/ into the main repo under hardware/v2/docs

2026-09-07 05:09:14 +02:00

README.md

docs: bring datasheet/ into the main repo under hardware/v2/docs

2026-09-07 05:09:14 +02:00

README.md

FPGA-Neural — Datasheet

Datasheet tecnico multicapitolo dell'engine FPGA-Neural, in italiano e inglese. Ricostruito a partire dal codice RTL, dalla documentazione e dai benchmark presenti nella repository (revisione A1, settembre 2026).

Struttura

docs/datasheet/
├── FPGA-Neural-Datasheet.pdf        ← PDF italiano (36 pagine)
├── FPGA-Neural-Datasheet.tex        ← sorgente principale (IT)
├── preamble.tex                     ← stili, palette, box, TikZ
├── chapters/                        ← 14 capitoli (IT)
└── en/
    ├── FPGA-Neural-Datasheet-EN.pdf ← PDF inglese (36 pagine)
    ├── FPGA-Neural-Datasheet-EN.tex ← sorgente principale (EN)
    ├── preamble.tex                 ← stili (EN)
    └── chapters/                    ← 14 capitoli (EN)

Compilazione

Serve una distribuzione LaTeX con pgfplots, tikz-timing, tcolorbox, ltablex, listings, babel.

# Italiano
cd docs/datasheet
pdflatex FPGA-Neural-Datasheet.tex
pdflatex FPGA-Neural-Datasheet.tex   # 2ª passata per indice e riferimenti

# Inglese
cd docs/datasheet/en
pdflatex FPGA-Neural-Datasheet-EN.tex
pdflatex FPGA-Neural-Datasheet-EN.tex

Nota sul pinout

Il capitolo Progetto hardware e mappa dei segnali riporta l'analisi completa segnale-per-segnale del top-level spi_neuron_top, con la colonna Ball compilata con assegnazioni CABGA381 reali (53 segnali, .lpf reale in synth/) e verificata da un place&route reale (nextpnr-ecp5, 0 errori di vincolo, Program finished normally) — non più auto-piazzate.