micheleandClaude Sonnet 5
0e73eb4726
Was a separate, untracked directory (DataSheet/) outside the repo. Renamed to lowercase and moved in as hardware/v2/docs/datasheet/, with its own .gitignore for LaTeX build byproducts (compiled PDFs stay tracked, .aux/.log/.toc/etc do not). Now versioned and shares this repo's own remote instead of living untracked on disk. Content: IT+EN LaTeX chapter sources, reference manufacturer PDFs, and compiled datasheet PDFs including the 2026-09-07 SDRAM upgrade addendum (AS4C32M16SB-7BIN part/pinout/timing) in the v2-en chapters. Note: hardware/v2/docs/DatasheetLatex/ (and the v1 sibling) is a separate, already-tracked, differently-structured LaTeX document that predates this move -- left untouched, not merged, since its chapter set and content differ and merging was not requested. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
96 lines
4.4 KiB
TeX
96 lines
4.4 KiB
TeX
\chapter{Compute datapath}
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\label{ch:datapath}
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\section{Bit-exact reuse of V1's arithmetic}
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\code{neural\_processor.v} implements the identical INT8/INT32 arithmetic
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chain as V1's own \code{neuron\_parallel.v}/\code{mac8.v}/\code{mac\_unit.v}
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--- verified bit-exact against V1's own modules, instantiated side-by-side
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in the same testbench, across 7 test cases including extreme INT8 values,
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back-to-back zero-gap tiles, and multi-tile jobs. What changed is the
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\emph{pipelining}, not the math.
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\begin{center}
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\begin{tikzpicture}[font=\scriptsize,node distance=3mm,start chain=going right,
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every node/.style={fnblock,minimum width=15mm,minimum height=8mm,on chain}]
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\node[fnblockT]{INT8\\$\times$\,INT8};
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\node{INT16\\product};
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\node{sign-ext\\INT32};
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\node[fnblockD]{accumulate\\INT32};
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\node{$+$ bias};
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\node[fnblockA]{activation};
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\node[fnblockT]{sat. INT8};
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\foreach \i [count=\j from 2] in {1,...,6}
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\draw[fnarrow] (chain-\i) -- (chain-\j);
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\end{tikzpicture}
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\end{center}
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\section{8-stage pipeline}
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\code{neural\_processor.v} is fully pipelined, throughput-oriented (one
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new tile accepted per cycle in steady state, given a continuous operand
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stream):
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\begin{center}
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\begin{tikzpicture}[font=\scriptsize,node distance=2.5mm,start chain=going below,
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every node/.style={on chain,fnblock,minimum width=64mm}]
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\node[fnblockA]{Stage 0 --- input alignment / register (\code{x0}, \code{w0})};
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\node{Stage 1 --- per-lane multiply (\code{P\_IN}$\times$\code{MULT18X18D})};
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\node{Stages 2..$(1{+}\log_2\text{P\_IN})$ --- balanced adder tree};
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\node[fnblockD]{accumulate (gated by job state, cleared at job start)};
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\node{$+$bias, activation select};
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\node[fnblockT]{INT8 saturation / output register};
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\foreach \i [count=\j from 2] in {1,...,5}
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\draw[fnarrow] (chain-\i) -- (chain-\j);
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\end{tikzpicture}
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\end{center}
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With \code{P\_IN}=8 the adder tree has 3 levels, giving an 8-stage pipeline
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overall. \code{tile\_last} is gated identically to \code{valid} at every
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stage (\code{last0 <= (operand\_valid \&\& operand\_ready) ? tile\_last :
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1'b0;}) --- an early draft left it ungated, letting a ``last'' tag
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propagate one cycle ahead of its own valid/data pair on jobs where
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\code{tile\_last} was asserted before \code{operand\_ready} rose (legal
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valid-before-ready producer behavior); found and fixed via a
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cycle-by-cycle dump of the pipeline's own internal valid/last signals,
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re-verified against the full 7-test regression.
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\section{Accumulator width: 24 vs.\ 32 bits}
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A real, 6-seed placement sweep (reusing already-synthesized netlists,
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real \code{nextpnr-ecp5} place\&route only) resolved an earlier
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single-seed measurement that had suggested \code{ACC\_WIDTH}=32 was
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marginally faster:
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\begin{tabularx}{\textwidth}{L{2.6cm} C{2.0cm} C{2.0cm} C{2.0cm} C{1.6cm}}
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\toprule
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\rowh \thd{ACC\_WIDTH} & \thd{mean Fmax} & \thd{min} & \thd{max} & \thd{stdev} \\
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\midrule
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32 & 170.12~MHz & 145.73 & 183.96 & 14.16 \\
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\rowa 24 & \textbf{180.71~MHz} & 175.16 & 185.49 & \textbf{4.21} \\
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\bottomrule
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\end{tabularx}
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\begin{center}\footnotesize\itshape\color{fnGrey}
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Real place\&route, P\_IN=8, 6 seeds each (default plus 5 explicit).\end{center}
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\begin{fnnote}[Why a single seed misled]
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Over 6 real placement seeds, \code{ACC\_WIDTH}=24 has both a higher mean
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Fmax ($+$6.2\%) and a much tighter seed-to-seed spread ($\approx$3.4$\times$
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tighter) than \code{ACC\_WIDTH}=32 --- combined with fewer LUT/FF/CCU2C at
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24 bits and identical bit-exact correctness, \code{ACC\_WIDTH}=24 is
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recommended for any new P\_IN=8 INT8 configuration, where product
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magnitudes never need more than 24 bits of accumulator headroom.
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\end{fnnote}
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\section{Activation and saturation}
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Identical encoding and bit-test logic to V1 (bilateral saturation for
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\code{ACT\_NONE}, positive-only for \code{ACT\_RELU}, both INT8-range).
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Every job dispatched by \code{dataflow\_core.v} currently hardcodes
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\code{job\_bias=0}, \code{job\_activation=ACT\_RELU} --- a documented
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simplification carried through every milestone since M4/M5, not yet
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exposed per-node by the Dependency Manager's own job descriptor.
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\begin{tabularx}{\textwidth}{L{2.6cm} C{1.4cm} Y}
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\toprule
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\rowh \thd{Encoding} & \thd{Value} & \thd{Behavior} \\
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\midrule
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\code{ACT\_NONE} & \code{2'd0} & Linear: bilateral saturation to $[-128,+127]$. \\
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\rowa \code{ACT\_RELU} & \code{2'd1} & $\max(0,x)$, positive saturation to $+127$ (used by every V2 job today). \\
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\bottomrule
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\end{tabularx}
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