micheleandCursor
8d2b85600f
Rename the core package to periscopex, update UI/docs/Docker/deploy defaults to periscope.michelebigi.it, and keep legacy version/storage key aliases so existing projects keep working. Co-authored-by: Cursor <cursoragent@cursor.com>
125 lines
3.8 KiB
Python
125 lines
3.8 KiB
Python
"""Regulator Iout margin and series-R IR drop — no invented IQ or traces."""
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from __future__ import annotations
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from backend.periscopex.models import (
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Component,
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ComponentConstraints,
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ComponentType,
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DesignGraph,
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Net,
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NetType,
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Pin,
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PinConnection,
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ResistorSpecs,
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SimpleComponentSpecs,
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)
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from backend.periscopex.power_margin_check import check_power_margin
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def _graph(components, nets):
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net_objs = {}
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for name, (ntype, volt, conns) in nets.items():
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net_objs[name] = Net(
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name=name, net_type=ntype, voltage=volt,
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pins=[PinConnection(component_ref=r, pin_number=str(p)) for r, p in conns],
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)
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return DesignGraph(components=components, nets=net_objs)
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def _cons():
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return {
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"LDOX": ComponentConstraints(
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mpn="LDOX", component_subtype="ic.power.ldo",
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pintable=[
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Pin(number=1, name="VIN"),
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Pin(number=2, name="VOUT"),
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Pin(number=3, name="GND"),
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],
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absolute_maximum_ratings=[], rules=[],
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)
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}
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def _ldo(values):
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return Component(
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reference="U1", value="", footprint="",
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component_type=ComponentType.IC, component_subtype="ic.power.ldo",
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mpn="LDOX",
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pins={"1": "VIN", "2": "VOUT", "3": "GND"},
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specs=SimpleComponentSpecs(specs_type="ic", component_subtype="ic.power.ldo", values=values),
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)
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def _mcu(iq=None):
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values = {} if iq is None else {"iq_a": iq}
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return Component(
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reference="U2", value="", footprint="",
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component_type=ComponentType.IC, mpn="MCU",
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pins={"1": "VOUT", "2": "GND"},
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specs=SimpleComponentSpecs(specs_type="ic", values=values) if values else None,
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)
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def test_load_over_iout_max_is_ps_pwr_001():
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g = _graph(
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{
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"U1": _ldo({"i_load_a": 0.4, "iout_max_a": 0.5}),
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"U2": _mcu(0.2),
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},
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{
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"VIN": (NetType.POWER, 5.0, [("U1", "1")]),
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"VOUT": (NetType.POWER, 3.3, [("U1", "2"), ("U2", "1")]),
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"GND": (NetType.GROUND, 0.0, [("U1", "3"), ("U2", "2")]),
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},
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)
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findings = check_power_margin(g, _cons())
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assert any(f.rule_id == "PE-PWR-001" and f.designator == "U1" for f in findings)
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def test_missing_iq_is_not_guessed_into_margin_fail():
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g = _graph(
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{
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"U1": _ldo({"iout_max_a": 0.1}),
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"U2": _mcu(None),
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},
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{
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"VIN": (NetType.POWER, 5.0, [("U1", "1")]),
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"VOUT": (NetType.POWER, 3.3, [("U1", "2"), ("U2", "1")]),
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"GND": (NetType.GROUND, 0.0, [("U1", "3"), ("U2", "2")]),
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},
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)
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assert check_power_margin(g, _cons()) == []
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def test_series_r_ir_drop_uses_i_load_not_trace():
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r = Component(
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reference="R1", value="1", footprint="",
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component_type=ComponentType.RESISTOR, mpn="R1",
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pins={"1": "USB", "2": "VIN"},
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specs=ResistorSpecs(value_ohms=1.0, value_formatted="1"),
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)
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g = _graph(
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{"U1": _ldo({"i_load_a": 0.5, "iout_max_a": 1.0}), "R1": r},
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{
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"USB": (NetType.POWER, 5.0, [("R1", "1")]),
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"VIN": (NetType.POWER, 5.0, [("R1", "2"), ("U1", "1")]),
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"VOUT": (NetType.POWER, 3.3, [("U1", "2")]),
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"GND": (NetType.GROUND, 0.0, [("U1", "3")]),
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},
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)
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findings = check_power_margin(g, _cons())
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assert any(f.designator == "R1" and f.rule_id == "PE-PWR-001" for f in findings)
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def test_no_series_r_does_not_invent_trace_drop():
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g = _graph(
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{"U1": _ldo({"i_load_a": 0.5, "iout_max_a": 1.0})},
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{
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"VIN": (NetType.POWER, 5.0, [("U1", "1")]),
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"VOUT": (NetType.POWER, 3.3, [("U1", "2")]),
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"GND": (NetType.GROUND, 0.0, [("U1", "3")]),
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},
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)
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assert check_power_margin(g, _cons()) == []
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