micheleandCursor
d47ad91cee
Stop LDO 3V3 groups from inheriting VSYS caps/filters, drop connector/switch noise, and align Power rails with domain membership. Co-authored-by: Cursor <cursoragent@cursor.com>
233 lines
8.2 KiB
Python
233 lines
8.2 KiB
Python
"""Layout F1 functional_groups on simple_project — topology only, no mm."""
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from __future__ import annotations
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import json
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from pathlib import Path
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from backend.pinscopex.functional_groups import build_functional_groups
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from backend.pinscopex.models import DesignGraph
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SIMPLE = Path(__file__).resolve().parents[1] / "simple_project"
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def _graph() -> DesignGraph:
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return DesignGraph.model_validate_json(
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(SIMPLE / "design_graph.json").read_text(encoding="utf-8"),
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)
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def test_simple_project_has_mcu_ldo_bridge_groups():
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report = build_functional_groups(_graph())
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assert report.objective == "routing"
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refs = {g.ref for g in report.groups}
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assert {"U1", "U2", "U3"} <= refs
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# No millimetre fields on the report model dump
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raw = json.loads(report.model_dump_json())
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blob = json.dumps(raw)
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assert "max_distance_mm" not in blob or all(
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r.get("max_distance_mm") is None
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for g in raw["groups"]
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for r in g.get("layout_rules") or []
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)
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def test_u3_owns_crystal_load_caps():
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report = build_functional_groups(_graph())
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u3 = next(g for g in report.groups if g.ref == "U3")
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sat = {s.ref: s.role_hint for s in u3.satellites}
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assert "X1" in sat
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assert sat["X1"] == "crystal"
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assert sat.get("C9") == "load_cap" or sat.get("C10") == "load_cap"
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assert "C9" in sat and "C10" in sat
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assert sat["C9"] == "load_cap"
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assert sat["C10"] == "load_cap"
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def test_u1_has_decoupling_or_bulk_on_rails():
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report = build_functional_groups(_graph())
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u1 = next(g for g in report.groups if g.ref == "U1")
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roles = {s.role_hint for s in u1.satellites}
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assert roles & {"decoupling", "bulk"}
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def test_domains_cover_all_ics():
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report = build_functional_groups(_graph())
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covered = {r for d in report.domains for r in d.ic_refs}
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assert covered == {"U1", "U2", "U3"}
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assert all(d.assemble_order for d in report.domains)
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def test_simple_project_splits_5v_and_3v3_domains():
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"""LDO bridges +5V/+3V3 electrically but domains follow primary rails."""
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report = build_functional_groups(_graph())
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by_rail = {d.power_nets[0]: set(d.ic_refs) for d in report.domains if d.power_nets}
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assert by_rail.get("+5V") == {"U2"}
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assert by_rail.get("+3V3") == {"U1", "U3"}
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assert len(report.domains) == 2
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def test_ldo_power_satellites_stay_on_primary_rail():
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"""LDO input-rail caps must not appear as primary-rail satellites."""
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from backend.pinscopex.models import (
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CapacitorSpecs,
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Component,
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ComponentType,
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DesignGraph,
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InductorSpecs,
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Net,
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NetType,
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PinConnection,
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)
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components = {
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"U1": Component(
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reference="U1", value="LDO", footprint="",
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component_type=ComponentType.IC,
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component_subtype="ic.power.ldo",
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pins={"1": "VSYS", "2": "3V3_DIGITAL", "3": "GND"},
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),
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"C_in": Component(
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reference="C_in", value="10u", footprint="",
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component_type=ComponentType.CAPACITOR,
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pins={"1": "VSYS", "2": "GND"},
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specs=CapacitorSpecs(value_farads=10e-6, value_formatted="10uF"),
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),
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"L1": Component(
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reference="L1", value="2.2u", footprint="",
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component_type=ComponentType.INDUCTOR,
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pins={"1": "VSYS", "2": "VSYS"},
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specs=InductorSpecs(value_henries=2.2e-6, value_formatted="2.2uH"),
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),
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"C_out": Component(
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reference="C_out", value="100n", footprint="",
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component_type=ComponentType.CAPACITOR,
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pins={"1": "3V3_DIGITAL", "2": "GND"},
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specs=CapacitorSpecs(value_farads=100e-9, value_formatted="100nF"),
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),
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"J1": Component(
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reference="J1", value="USB", footprint="",
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component_type=ComponentType.CONNECTOR,
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pins={"1": "3V3_DIGITAL", "2": "GND"},
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),
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}
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nets = {
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"VSYS": Net(
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name="VSYS", net_type=NetType.POWER,
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pins=[
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PinConnection(component_ref="U1", pin_number="1"),
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PinConnection(component_ref="C_in", pin_number="1"),
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PinConnection(component_ref="L1", pin_number="1"),
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],
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),
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"3V3_DIGITAL": Net(
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name="3V3_DIGITAL", net_type=NetType.POWER,
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pins=[
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PinConnection(component_ref="U1", pin_number="2"),
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PinConnection(component_ref="C_out", pin_number="1"),
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PinConnection(component_ref="J1", pin_number="1"),
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],
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),
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"GND": Net(
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name="GND", net_type=NetType.GROUND,
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pins=[
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PinConnection(component_ref="U1", pin_number="3"),
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PinConnection(component_ref="C_in", pin_number="2"),
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PinConnection(component_ref="C_out", pin_number="2"),
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PinConnection(component_ref="J1", pin_number="2"),
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],
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),
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}
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report = build_functional_groups(DesignGraph(components=components, nets=nets))
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u1 = next(g for g in report.groups if g.ref == "U1")
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sat = {s.ref: s.role_hint for s in u1.satellites}
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assert "C_out" in sat
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assert "C_in" not in sat
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assert "L1" not in sat
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assert "J1" not in sat
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def test_multi_rail_board_does_not_collapse_to_one_domain():
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"""Charger→LDO→MCU must not become a single domain via shared POWER nets."""
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from backend.pinscopex.models import (
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Component,
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ComponentType,
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DesignGraph,
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Net,
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NetType,
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PinConnection,
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)
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components = {
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"U1": Component(
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reference="U1", value="BQ25896", footprint="",
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component_type=ComponentType.IC,
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component_subtype="ic.power.battery_charger",
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pins={"1": "VBUS", "2": "VSYS", "3": "GND"},
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),
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"U2": Component(
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reference="U2", value="AP2112", footprint="",
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component_type=ComponentType.IC,
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component_subtype="ic.power.ldo",
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pins={"1": "VSYS", "2": "3V3_DIGITAL", "3": "GND"},
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),
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"U3": Component(
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reference="U3", value="ESP32", footprint="",
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component_type=ComponentType.IC,
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component_subtype="ic.rf.wifi_module",
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pins={"1": "3V3_DIGITAL", "2": "GND"},
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),
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"U4": Component(
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reference="U4", value="SRV05", footprint="",
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component_type=ComponentType.IC,
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component_subtype="ic.protection.esd",
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pins={"1": "VBUS", "2": "GND"},
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),
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}
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nets = {
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"VBUS": Net(
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name="VBUS", net_type=NetType.POWER,
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pins=[
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PinConnection(component_ref="U1", pin_number="1"),
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PinConnection(component_ref="U4", pin_number="1"),
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],
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),
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"VSYS": Net(
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name="VSYS", net_type=NetType.POWER,
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pins=[
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PinConnection(component_ref="U1", pin_number="2"),
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PinConnection(component_ref="U2", pin_number="1"),
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],
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),
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"3V3_DIGITAL": Net(
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name="3V3_DIGITAL", net_type=NetType.POWER,
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pins=[
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PinConnection(component_ref="U2", pin_number="2"),
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PinConnection(component_ref="U3", pin_number="1"),
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],
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),
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"GND": Net(
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name="GND", net_type=NetType.GROUND,
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pins=[
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PinConnection(component_ref="U1", pin_number="3"),
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PinConnection(component_ref="U2", pin_number="3"),
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PinConnection(component_ref="U3", pin_number="2"),
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PinConnection(component_ref="U4", pin_number="2"),
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],
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),
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}
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report = build_functional_groups(DesignGraph(components=components, nets=nets))
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by_rail = {d.power_nets[0]: set(d.ic_refs) for d in report.domains if d.power_nets}
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assert len(report.domains) >= 3
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assert by_rail.get("VBUS") == {"U4"}
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assert by_rail.get("VSYS") == {"U1"}
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assert by_rail.get("3V3_DIGITAL") == {"U2", "U3"}
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def test_build_placement_plan_alias():
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from backend.pinscopex.functional_groups import build_placement_plan
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report = build_placement_plan(_graph())
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assert report.objective == "routing"
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assert {g.ref for g in report.groups} >= {"U1", "U2", "U3"}
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