michele
4df04df5d4
Add /api/library datasheet import and component GET/PUT with no exam. Reorganize pytest into datasheet, library, schematic, PCB, and AF+AI. Document Rust criteria (none chosen; no rustup) and coding conformity.
424 lines
14 KiB
Python
424 lines
14 KiB
Python
"""Fase B close-out: BOM↔PCB↔datasheet, SPOF, EMI FACT, gated Tj, SI refresh."""
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from __future__ import annotations
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from backend.periscopex.layout_rules import needs_layout_rules_refresh
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from backend.periscopex.models import (
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AbsMaxRating,
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Component,
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ComponentConstraints,
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ComponentType,
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DesignGraph,
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InductorSpecs,
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LayoutFootprint,
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LayoutGraph,
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LayoutPad,
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LayoutVia,
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LayoutZone,
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Net,
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NetType,
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PackageInfo,
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Pin,
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PinConnection,
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SimpleComponentSpecs,
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)
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def test_si_refresh_when_old_extract_has_only_decoupling():
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assert needs_layout_rules_refresh(
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{
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"model_version": "1.10.0",
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"layout_rules": [{"kind": "decoupling_proximity", "max_distance_mm": 2}],
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},
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min_scan_version="1.12.0",
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)
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assert not needs_layout_rules_refresh(
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{
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"model_version": "1.12.0",
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"layout_rules": [],
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},
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min_scan_version="1.12.0",
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)
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assert not needs_layout_rules_refresh(
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{
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"model_version": "1.10.0",
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"layout_rules": [{"kind": "impedance", "zdiff_ohm": 90}],
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},
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min_scan_version="1.12.0",
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)
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assert not needs_layout_rules_refresh(
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{
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"model_version": "1.12.0",
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"layout_rules": [{"kind": "series_resistor", "value_ohms": 10000}],
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},
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min_scan_version="1.12.0",
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)
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assert needs_layout_rules_refresh(
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{
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"model_version": "1.12.0",
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"layout_rules": [{
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"kind": "series_resistor",
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"value_ohms": 10000,
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"note": "EN RC 10 kΩ / 1 µF",
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}],
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},
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min_scan_version="1.13.0",
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)
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assert not needs_layout_rules_refresh(
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{
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"model_version": "1.12.0",
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"layout_rules": [{"kind": "impedance", "net_class": "usb2", "zdiff_ohm": 90}],
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},
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min_scan_version="1.13.0",
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)
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assert not needs_layout_rules_refresh(
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{
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"model_version": "1.12.0",
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"layout_rules": [],
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},
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min_scan_version="1.13.0",
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)
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def test_si_extract_needed_skips_board_ics_only_not_shared_library():
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from backend.services.pcb_pipeline import si_extract_needed_skips
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graph = DesignGraph(
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components={
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"U5": Component(
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reference="U5", value="ESP32-C6-WROOM-1", footprint="",
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component_type=ComponentType.IC, mpn="ESP32-C6-WROOM-1",
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pins={"1": "EN"},
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),
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"J1": Component(
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reference="J1", value="USB-C", footprint="",
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component_type=ComponentType.CONNECTOR, mpn="TYPE-C-31-M-12",
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pins={},
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),
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},
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nets={},
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)
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fresh = ComponentConstraints(
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mpn="ESP32-C6-WROOM-1",
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model_version="1.13.0",
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pintable=[Pin(number="1", name="EN")],
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absolute_maximum_ratings=[],
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rules=[],
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layout_rules=[{"kind": "decoupling_proximity", "pin": "EN"}],
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)
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stale_lib = ComponentConstraints(
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mpn="LAN8720A",
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model_version="1.5.0",
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pintable=[Pin(number="1", name="TXP")],
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absolute_maximum_ratings=[],
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rules=[],
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layout_rules=[],
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)
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stale_board = fresh.model_copy(update={"model_version": "1.5.0", "layout_rules": []})
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assert si_extract_needed_skips(
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graph, {"ESP32-C6-WROOM-1": fresh, "LAN8720A": stale_lib}, "1.13.0",
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) == []
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skips = si_extract_needed_skips(
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graph, {"ESP32-C6-WROOM-1": stale_board, "LAN8720A": stale_lib}, "1.13.0",
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)
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assert len(skips) == 1
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assert skips[0]["designator"] == "U5"
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assert "LAN8720A" not in skips[0]["designator"]
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def test_package_family_mismatch_is_pe_bom_010():
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from backend.periscopex.bom_pcb_check import check_bom_pcb_datasheet
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cons = ComponentConstraints(
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mpn="IC1",
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package_info=PackageInfo(
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base_family="MSP", package="LQFP-48", pin_count=48,
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),
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pintable=[Pin(number=str(i), name=f"P{i}") for i in range(1, 49)],
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absolute_maximum_ratings=[],
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rules=[],
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)
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graph = DesignGraph(
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components={
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"U1": Component(
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reference="U1", value="IC", footprint="Package_DFN_QFN:QFN-16-1EP",
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component_type=ComponentType.IC, mpn="IC1",
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pins={str(i): "GND" for i in range(1, 17)},
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),
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},
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nets={"GND": Net(name="GND", net_type=NetType.GROUND, pins=[])},
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schematic_fields={"U1": {"footprint": "Package_DFN_QFN:QFN-16-1EP"}},
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bom_fields={"U1": {"footprint": "QFN-16"}},
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)
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layout = LayoutGraph(
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footprints={
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"U1": LayoutFootprint(
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reference="U1", footprint="Package_DFN_QFN:QFN-16-1EP_3x3mm",
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x=0, y=0, layer="F.Cu",
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pads=[LayoutPad(number=str(i), x=0, y=0, net="GND") for i in range(1, 17)],
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),
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},
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)
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findings = check_bom_pcb_datasheet(graph, {"IC1": cons}, layout)
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ids = {f.rule_id for f in findings}
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assert "PE-BOM-010" in ids
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assert "PE-BOM-011" in ids
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assert all(f.status == "ERROR" for f in findings if f.rule_id in {"PE-BOM-010", "PE-BOM-011"})
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def test_abs_max_voltage_and_temp_and_current():
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from backend.periscopex.bom_pcb_check import check_bom_pcb_datasheet
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cons = ComponentConstraints(
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mpn="LDO1",
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package_info=PackageInfo(base_family="SPX", package="SOT-23-5", pin_count=5),
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pintable=[
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Pin(number="1", name="VIN"),
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Pin(number="2", name="GND"),
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Pin(number="5", name="VOUT"),
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],
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absolute_maximum_ratings=[
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AbsMaxRating(parameter="VIN", min=None, max=4.0, unit="V", source_page=3),
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AbsMaxRating(parameter="TJ", min=None, max=125, unit="C", source_page=3),
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AbsMaxRating(parameter="IOUT", min=None, max=0.1, unit="A", source_page=4),
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],
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rules=[],
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)
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graph = DesignGraph(
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components={
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"U1": Component(
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reference="U1", value="LDO", footprint="Package_TO_SOT_SMD:SOT-23-5",
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component_type=ComponentType.IC, mpn="LDO1",
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pins={"1": "VIN", "2": "GND", "5": "VOUT"},
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specs=SimpleComponentSpecs(
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specs_type="discrete",
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values={"i_load_a": 0.5, "ta_max_c": 150},
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),
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),
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},
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nets={
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"VIN": Net(
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name="VIN", net_type=NetType.POWER, voltage=5.0,
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pins=[PinConnection(component_ref="U1", pin_number="1")],
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),
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"GND": Net(name="GND", net_type=NetType.GROUND, pins=[]),
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"VOUT": Net(name="VOUT", net_type=NetType.POWER, voltage=3.3, pins=[]),
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},
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)
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findings = check_bom_pcb_datasheet(graph, {"LDO1": cons}, None)
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ids = {f.rule_id for f in findings}
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assert "PE-BOM-012" in ids
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assert "PE-BOM-013" in ids
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assert "PE-BOM-014" in ids
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def test_inductor_current_rating():
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from backend.periscopex.bom_pcb_check import check_bom_pcb_datasheet
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graph = DesignGraph(
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components={
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"L1": Component(
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reference="L1", value="2.2uH", footprint="",
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component_type=ComponentType.INDUCTOR, mpn="IND1",
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pins={"1": "SW", "2": "VOUT"},
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specs=InductorSpecs(
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value_henries=2.2e-6,
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value_formatted="2.2uH",
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current_rating_a="0.2",
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),
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),
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},
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nets={},
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)
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graph.components["L1"].specs # type: ignore
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# I_load on the inductor itself
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graph.components["L1"] = graph.components["L1"].model_copy(
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update={"specs": InductorSpecs(
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value_henries=2.2e-6, value_formatted="2.2uH", current_rating_a="0.2",
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)}
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)
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# specs_values reads SimpleComponentSpecs.values — inductor uses current_rating_a
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findings = check_bom_pcb_datasheet(graph, {}, None)
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# Without i_load on inductor specs, skip.
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assert all(f.rule_id != "PE-BOM-014" for f in findings)
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def test_spof_review_single_ldo():
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from backend.periscopex.finding_engine import complete_finding
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from backend.periscopex.spof_check import check_spof
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cons = ComponentConstraints(
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mpn="LDO1",
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pintable=[Pin(number="1", name="VIN"), Pin(number="2", name="VOUT")],
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absolute_maximum_ratings=[],
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rules=[],
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)
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graph = DesignGraph(
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components={
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"U1": Component(
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reference="U1", value="LDO", footprint="",
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component_type=ComponentType.IC, mpn="LDO1",
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component_subtype="ic.power.ldo",
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pins={"1": "VIN", "2": "+3V3"},
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),
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"U2": Component(
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reference="U2", value="MCU", footprint="",
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component_type=ComponentType.IC, mpn="MCU",
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pins={"1": "+3V3"},
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),
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"U3": Component(
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reference="U3", value="PHY", footprint="",
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component_type=ComponentType.IC, mpn="PHY",
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pins={"1": "+3V3"},
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),
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},
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nets={
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"VIN": Net(name="VIN", net_type=NetType.POWER, pins=[]),
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"+3V3": Net(
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name="+3V3", net_type=NetType.POWER,
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pins=[
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PinConnection(component_ref="U1", pin_number="2"),
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PinConnection(component_ref="U2", pin_number="1"),
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PinConnection(component_ref="U3", pin_number="1"),
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],
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),
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},
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)
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findings = check_spof(graph, {"LDO1": cons})
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assert findings
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assert findings[0].rule_id == "PE-SPOF-001"
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complete_finding(findings[0])
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assert findings[0].finding_class == "REVIEW"
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assert findings[0].status != "ERROR"
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def test_emi_only_with_datasheet_fact():
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from backend.periscopex.emi_check import check_emi
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cons = ComponentConstraints(
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mpn="PHY",
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pintable=[Pin(number="1", name="USB_DP")],
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absolute_maximum_ratings=[],
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rules=[],
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layout_rules=[{
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"kind": "keepout",
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"note": "Place a common-mode choke on the USB pair",
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"source_page": 22,
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}],
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)
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graph = DesignGraph(
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components={
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"U2": Component(
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reference="U2", value="PHY", footprint="",
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component_type=ComponentType.IC, mpn="PHY",
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pins={"1": "USB_DP"},
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),
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},
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nets={
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"USB_DP": Net(
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name="USB_DP", net_type=NetType.SIGNAL,
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pins=[PinConnection(component_ref="U2", pin_number="1")],
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),
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},
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)
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findings = check_emi(graph, {"PHY": cons}, None)
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assert findings and findings[0].rule_id == "PE-EMI-001"
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cons2 = cons.model_copy(update={"layout_rules": []})
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assert check_emi(graph, {"PHY": cons2}, None) == []
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def test_tj_when_theta_copper_vias_exist():
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from backend.periscopex.pcb_power_thermal import check_pcb_junction_temp
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from backend.periscopex.models import LayoutSegment, LayoutStackup
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cons = ComponentConstraints(
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mpn="LDO1",
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pintable=[Pin(number="1", name="VIN"), Pin(number="2", name="VOUT")],
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absolute_maximum_ratings=[],
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rules=[],
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)
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graph = DesignGraph(
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components={
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"U1": Component(
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reference="U1", value="LDO", footprint="",
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component_type=ComponentType.IC, mpn="LDO1",
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component_subtype="ic.power.ldo",
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pins={"1": "VIN", "2": "VOUT"},
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specs=SimpleComponentSpecs(
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specs_type="discrete",
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values={"i_load_a": 0.5, "theta_ja": 50, "tj_max": 150},
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),
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),
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},
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nets={
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"VIN": Net(
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name="VIN", net_type=NetType.POWER, voltage=5.0,
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pins=[PinConnection(component_ref="U1", pin_number="1")],
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),
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"VOUT": Net(
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name="VOUT", net_type=NetType.POWER, voltage=3.3,
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pins=[PinConnection(component_ref="U1", pin_number="2")],
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),
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},
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)
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layout = LayoutGraph(
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stackup=LayoutStackup(copper_layers=["F.Cu"], dielectrics=[], copper_thickness_mm=0.035),
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footprints={
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"U1": LayoutFootprint(
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reference="U1", x=0, y=0, layer="F.Cu",
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courtyard=[(-2, -2), (2, -2), (2, 2), (-2, 2)],
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pads=[LayoutPad(number="2", x=0, y=0, net="VOUT")],
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),
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},
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segments=[LayoutSegment(start=(0, 0), end=(5, 0), width=0.5, layer="F.Cu", net="VOUT")],
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vias=[LayoutVia(x=0.1, y=0.1, net="GND", drill=0.3)],
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zones=[LayoutZone(
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net="GND", layer="F.Cu",
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outlines=[[(-3, -3), (3, -3), (3, 3), (-3, 3)]],
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)],
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)
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findings = check_pcb_junction_temp(graph, {"LDO1": cons}, layout)
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assert findings and findings[0].rule_id == "PE-THM-002"
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assert findings[0].evidence_status == "SUFFICIENT"
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assert "Tj" in findings[0].finding
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assert findings[0].status == "INFO"
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def test_tj_insufficient_without_theta():
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from backend.periscopex.pcb_power_thermal import check_pcb_junction_temp
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cons = ComponentConstraints(
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mpn="LDO1",
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pintable=[Pin(number="1", name="VIN"), Pin(number="2", name="VOUT")],
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absolute_maximum_ratings=[],
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rules=[],
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)
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graph = DesignGraph(
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components={
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"U1": Component(
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reference="U1", value="LDO", footprint="",
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component_type=ComponentType.IC, mpn="LDO1",
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pins={"1": "VIN", "2": "VOUT"},
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specs=SimpleComponentSpecs(
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specs_type="discrete",
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values={"i_load_a": 0.5},
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),
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),
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},
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nets={
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"VIN": Net(
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name="VIN", net_type=NetType.POWER, voltage=5.0,
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pins=[PinConnection(component_ref="U1", pin_number="1")],
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),
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"VOUT": Net(
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name="VOUT", net_type=NetType.POWER, voltage=3.3,
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pins=[PinConnection(component_ref="U1", pin_number="2")],
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),
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},
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)
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layout = LayoutGraph(footprints={})
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findings = check_pcb_junction_temp(graph, {"LDO1": cons}, layout)
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assert findings and findings[0].rule_id == "PE-THM-002"
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assert findings[0].evidence_status == "INSUFFICIENT"
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assert findings[0].status == "INFO"
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