michele
6d9d21a023
POST /api/library/datasheets now writes an IC inbox card or a passive/discrete model. Empty pintables never enter library/extracted. AF Board+AI runs after unchanged run_pcb_checks (PE-SI / HF line stay).
206 lines
6.7 KiB
Python
206 lines
6.7 KiB
Python
"""AF board + AI: hypotheses of probable HF issues, then deterministic checks.
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Does not replace run_pcb_checks. Not DRC. Never invents Z.
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"""
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from __future__ import annotations
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from backend.periscopex.af_ai_hf import (
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HfHypothesis,
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append_investigated,
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hypotheses_from_rows,
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investigate_hf_hypotheses,
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)
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from backend.periscopex.hf_line_check import check_hf_lines
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from backend.periscopex.models import (
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Component,
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ComponentConstraints,
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ComponentType,
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DesignGraph,
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LayoutFootprint,
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LayoutGraph,
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LayoutPad,
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LayoutSegment,
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LayoutStackup,
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LayoutDielectric,
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Net,
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NetType,
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Pin,
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PinConnection,
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)
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from backend.periscopex.pcb_checks import run_pcb_checks
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def _ic(ref: str, pins: dict[str, str], *, mpn: str = "PHY") -> Component:
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return Component(
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reference=ref, value=mpn, footprint="",
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component_type=ComponentType.IC, mpn=mpn, pins=pins,
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)
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def _net(name: str, *pairs: tuple[str, str]) -> Net:
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return Net(
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name=name, net_type=NetType.SIGNAL,
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pins=[PinConnection(component_ref=r, pin_number=p) for r, p in pairs],
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)
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def _usb_graph() -> DesignGraph:
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return DesignGraph(
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components={
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"U1": _ic("U1", {"1": "USB_D+", "2": "USB_D-"}),
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"J2": Component(
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reference="J2", value="USB_C", footprint="",
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component_type=ComponentType.CONNECTOR,
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pins={"A6": "USB_D+", "A7": "USB_D-"},
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),
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},
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nets={
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"USB_D+": _net("USB_D+", ("U1", "1"), ("J2", "A6")),
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"USB_D-": _net("USB_D-", ("U1", "2"), ("J2", "A7")),
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},
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)
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def _fp(ref: str, pads: list[LayoutPad], x: float = 0.0) -> LayoutFootprint:
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return LayoutFootprint(reference=ref, footprint="P", x=x, y=0.0, pads=pads)
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def _stub_layout() -> LayoutGraph:
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return LayoutGraph(
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footprints={
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"U1": _fp("U1", [LayoutPad(number="1", x=0.0, y=0.0, net="USB_D+")]),
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"J2": _fp("J2", [LayoutPad(number="A6", x=10.0, y=0.0, net="USB_D+")], x=10.0),
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},
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segments=[
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LayoutSegment(start=(0, 0), end=(10, 0), width=0.2, layer="F.Cu", net="USB_D+"),
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LayoutSegment(start=(10, 0), end=(10, 3), width=0.2, layer="F.Cu", net="USB_D+"),
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],
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)
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def _stub_constraints() -> dict:
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return {
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"PHY": ComponentConstraints(
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mpn="PHY", pintable=[Pin(number="1", name="D+")],
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absolute_maximum_ratings=[], rules=[],
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layout_rules=[{
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"kind": "stub", "net_class": "usb2", "max_distance_mm": 1.0,
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"note": "USB stub < 1 mm", "source_page": 12,
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}],
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),
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}
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def test_ai_stub_flag_then_deterministic_pe_si_007():
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graph = _usb_graph()
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layout = _stub_layout()
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cons = _stub_constraints()
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flags = [HfHypothesis(net="USB_D+", issue_class="stub", why="looks long")]
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out = investigate_hf_hypotheses(graph, cons, layout, flags)
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codes = [f.rule_id for f in out]
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assert "PE-SI-007" in codes
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hit = next(f for f in out if f.rule_id == "PE-SI-007")
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assert "FAIL" in hit.finding
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assert hit.evidence_status == "SUFFICIENT"
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def test_ai_z0_flag_without_stackup_is_insufficient_no_ohm():
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graph = _usb_graph()
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layout = _stub_layout()
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flags = [HfHypothesis(net="USB_D+", issue_class="z0", why="probably 90 ohm")]
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out = investigate_hf_hypotheses(graph, {}, layout, flags)
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assert len(out) == 1
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f = out[0]
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assert f.rule_id == "PE-AF-001"
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assert f.evidence_status == "INSUFFICIENT"
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assert "90" not in f.finding
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assert "50" not in f.finding
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assert "Ω" not in f.finding and "ohm" not in f.finding.lower()
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def test_ai_flag_on_missing_superspeed_net_is_silence():
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graph = _usb_graph()
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layout = _stub_layout()
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flags = [HfHypothesis(net="USB3_SSTX_P", issue_class="stub", why="SS pair")]
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out = investigate_hf_hypotheses(graph, _stub_constraints(), layout, flags)
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assert out == []
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def test_run_pcb_checks_still_finds_stub_without_af_ai():
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"""AF+AI is extra: the PCB check list must still emit PE-SI-007 alone."""
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graph = _usb_graph()
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layout = _stub_layout()
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pcb = run_pcb_checks(graph, _stub_constraints(), layout)
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assert any(f.rule_id == "PE-SI-007" for f in pcb)
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hf = check_hf_lines(graph, _stub_constraints(), layout)
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assert any(f.rule_id == "PE-SI-007" for f in hf)
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def test_z0_with_stackup_does_not_invent_ohm_number():
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graph = _usb_graph()
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layout = _stub_layout()
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layout.stackup = LayoutStackup(
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copper_layers=["F.Cu", "B.Cu"],
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dielectrics=[LayoutDielectric(name="core", er=4.5, height_mm=0.15)],
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)
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flags = [HfHypothesis(net="USB_D+", issue_class="z0", why="check Z0")]
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out = investigate_hf_hypotheses(graph, {}, layout, flags)
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for f in out:
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assert "50 Ω" not in (f.finding or "")
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assert "90 Ω" not in (f.finding or "")
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def test_append_investigated_keeps_pcb_checks_and_adds_pe_af():
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graph = _usb_graph()
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layout = _stub_layout()
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cons = _stub_constraints()
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pcb = run_pcb_checks(graph, cons, layout)
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n_si = sum(1 for f in pcb if f.rule_id == "PE-SI-007")
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assert n_si >= 1
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flags = [
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HfHypothesis(net="USB_D+", issue_class="stub", why="looks long"),
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HfHypothesis(net="USB_D+", issue_class="z0", why="probably 90 ohm"),
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]
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added = append_investigated(pcb, graph, cons, layout, flags)
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assert any(f.rule_id == "PE-AF-001" for f in added)
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assert sum(1 for f in pcb if f.rule_id == "PE-SI-007") == n_si
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assert "si_check" in _pcb_checks_source()
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assert "hf_line" in _pcb_checks_source()
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def test_hypotheses_from_rows_drops_unknown_class():
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rows = [
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{"net": "USB_D+", "issue_class": "stub", "why": "x"},
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{"net": "USB_D+", "issue_class": "clearance", "why": "drc"},
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{"net": "", "issue_class": "z0", "why": "empty"},
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]
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hyps = hypotheses_from_rows(rows)
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assert len(hyps) == 1
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assert hyps[0].issue_class == "stub"
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def test_pcb_pipeline_af_ai_is_after_run_pcb_checks():
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import inspect
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from backend.periscopex import pcb_checks
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from backend.services import pcb_pipeline
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src = inspect.getsource(pcb_pipeline.run_pcb_pipeline)
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assert "run_pcb_checks" in src
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assert "_run_af_ai_section" in src
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assert src.find("run_pcb_checks") < src.find("_run_af_ai_section")
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checks = inspect.getsource(pcb_checks.run_pcb_checks)
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assert '("si_check"' in checks or '"si_check"' in checks
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assert '"hf_line"' in checks
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assert "af_ai" not in checks
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assert "investigate_hf_hypotheses" not in checks
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def _pcb_checks_source() -> str:
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import inspect
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from backend.periscopex.pcb_checks import run_pcb_checks
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return inspect.getsource(run_pcb_checks)
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