michele
7a32c552bb
Partial layouts still use MODE=pcb. Missing copper is INSUFFICIENT or
skipped, never Euclidean stand-in tracks. Via≠Pad unchanged. DELETE
/api/projects/{id} is owner-only with a dashboard confirm dialog.
693 lines
23 KiB
Python
693 lines
23 KiB
Python
"""PCB review checks, inventory, report merge — no invented millimetres."""
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from __future__ import annotations
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from tests.paths import SIMPLE_PROJECT, TAXONOMY
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from pathlib import Path
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from backend.periscopex.functional_groups import FunctionalGroupsReport, PlacementDomain, PlacementIcGroup
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from backend.periscopex.models import (
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Component,
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ComponentType,
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DesignGraph,
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LayoutFootprint,
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LayoutGraph,
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LayoutPad,
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LayoutSegment,
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Net,
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NetType,
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)
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from backend.periscopex.pcb_checks import (
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assign_pcb_finding_ids,
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merge_schema_pcb_reports,
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run_pcb_checks,
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)
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from backend.periscopex.pcb_inventory import build_pcb_inventory
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from backend.periscopex.pcb_net_match import check_pcb_net_match
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from backend.periscopex.pcb_review import build_pcb_layout_context
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from backend.services.projects import ProjectMeta, STATUS_QUEUED, STATUS_RUNNING
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SIMPLE = SIMPLE_PROJECT
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def _graph() -> DesignGraph:
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return DesignGraph.model_validate_json(
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(SIMPLE / "design_graph.json").read_text()
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)
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def test_pad_net_mismatch_is_pe_lay_001():
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graph = DesignGraph(
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components={
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"U1": Component(
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reference="U1", value="", footprint="",
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component_type=ComponentType.IC, mpn="X",
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pins={"1": "GND"},
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),
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},
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nets={
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"GND": Net(name="GND", net_type=NetType.GROUND, pins=[]),
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"+3V3": Net(name="+3V3", net_type=NetType.POWER, pins=[]),
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},
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)
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layout = LayoutGraph(
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footprints={
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"U1": LayoutFootprint(
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reference="U1", x=0, y=0, layer="F.Cu",
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pads=[LayoutPad(number="1", x=0, y=0, net="+3V3")],
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),
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},
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)
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findings = check_pcb_net_match(graph, layout)
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assert len(findings) == 1
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assert findings[0].rule_id == "PE-LAY-001"
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assert findings[0].status == "ERROR"
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assert findings[0].recommendation
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assert "Reconnect pad" in findings[0].recommendation
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def test_kicad_hierarchy_slash_is_one_sync_finding_not_per_pad():
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"""PCB /X vs schematic X (Emmaforo table) — one PE-LAY-003, pads treated as same net."""
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from backend.periscopex.pcb_net_match import kicad_nets_match
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pairs = [
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("/ESP32_EN", "ESP32_EN"),
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("/ESP_32_BOOT", "ESP_32_BOOT"),
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("/REGN", "REGN"),
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("/LED_SDATA", "LED_SDATA"),
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("/power/REGN", "REGN"),
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]
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for pcb, sch in pairs:
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assert kicad_nets_match(pcb, sch), (pcb, sch)
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assert not kicad_nets_match("/sheet1/CLK", "/sheet2/CLK")
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assert not kicad_nets_match("/ESP32_EN", "ESP32_BOOT")
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pins = {
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"1": "ESP32_EN",
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"2": "ESP_32_BOOT",
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"3": "REGN",
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"4": "LED_SDATA",
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}
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graph = DesignGraph(
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components={
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"U1": Component(
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reference="U1", value="", footprint="",
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component_type=ComponentType.IC, mpn="ESP",
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pins=pins,
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),
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},
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nets={n: Net(name=n, net_type=NetType.SIGNAL, pins=[]) for n in pins.values()},
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)
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layout = LayoutGraph(
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footprints={
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"U1": LayoutFootprint(
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reference="U1", x=0, y=0, layer="F.Cu",
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pads=[
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LayoutPad(number="1", x=0, y=0, net="/ESP32_EN"),
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LayoutPad(number="2", x=1, y=0, net="/ESP_32_BOOT"),
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LayoutPad(number="3", x=2, y=0, net="/REGN"),
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LayoutPad(number="4", x=3, y=0, net="/LED_SDATA"),
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],
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),
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},
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)
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findings = check_pcb_net_match(graph, layout)
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assert [f.rule_id for f in findings] == ["PE-LAY-003"]
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assert findings[0].status == "INFO"
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assert "individual pads" in findings[0].recommendation.lower() or "Do not retouch" in findings[0].recommendation
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assert "Won't fix" not in findings[0].recommendation
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assert "Reconnect pad" not in findings[0].recommendation
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def test_hierarchy_plus_real_mismatch_keeps_only_real_pe_lay_001():
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graph = DesignGraph(
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components={
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"U1": Component(
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reference="U1", value="", footprint="",
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component_type=ComponentType.IC, mpn="X",
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pins={"1": "ESP32_EN", "2": "GND"},
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),
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},
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nets={
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"ESP32_EN": Net(name="ESP32_EN", net_type=NetType.SIGNAL, pins=[]),
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"GND": Net(name="GND", net_type=NetType.GROUND, pins=[]),
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"+3V3": Net(name="+3V3", net_type=NetType.POWER, pins=[]),
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},
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)
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layout = LayoutGraph(
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footprints={
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"U1": LayoutFootprint(
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reference="U1", x=0, y=0, layer="F.Cu",
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pads=[
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LayoutPad(number="1", x=0, y=0, net="/ESP32_EN"),
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LayoutPad(number="2", x=1, y=0, net="+3V3"),
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],
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),
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},
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)
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findings = check_pcb_net_match(graph, layout)
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assert [f.rule_id for f in findings] == ["PE-LAY-001"]
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assert findings[0].pins == ["2"]
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assert "+3V3" in findings[0].finding
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def test_missing_footprint_is_pe_lay_002():
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graph = DesignGraph(
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components={
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"R1": Component(
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reference="R1", value="10k", footprint="",
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component_type=ComponentType.RESISTOR, mpn="",
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pins={"1": "GND"},
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),
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},
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nets={"GND": Net(name="GND", net_type=NetType.GROUND, pins=[])},
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)
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layout = LayoutGraph(footprints={
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"U9": LayoutFootprint(reference="U9", x=0, y=0, layer="F.Cu"),
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})
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findings = check_pcb_net_match(graph, layout)
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assert any(f.rule_id == "PE-LAY-002" for f in findings)
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assert all(f.recommendation for f in findings)
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def test_run_pcb_checks_assigns_pcb_ids_and_recommendations():
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from tests.test_placement_check import _xtal_cons, _x1_c9_layout
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from backend.periscopex.models import LayoutSegment
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segs = [
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LayoutSegment(start=(0.0, 0.0), end=(10.0, 0.0), width=0.2, layer="F.Cu", net="/HFXIN"),
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]
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findings = run_pcb_checks(
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_graph(),
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_xtal_cons(max_distance_mm=2.0),
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_x1_c9_layout(cap_x=10.0, segments=segs),
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)
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plc = [f for f in findings if f.rule_id == "PE-PLC-001"]
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assert plc
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assert plc[0].finding_id.startswith("PCB-")
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assert plc[0].recommendation
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def test_close_decoupling_has_no_plc_001():
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from tests.test_placement_check import _xtal_cons, _x1_c9_layout
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from backend.periscopex.models import LayoutSegment
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segs = [
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LayoutSegment(start=(0.0, 0.0), end=(0.5, 0.0), width=0.2, layer="F.Cu", net="/HFXIN"),
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]
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findings = run_pcb_checks(
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_graph(),
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_xtal_cons(max_distance_mm=2.0),
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_x1_c9_layout(cap_x=0.5, segments=segs),
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)
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assert all(f.rule_id != "PE-PLC-001" for f in findings)
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def test_inventory_lists_net_length_and_pair():
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layout = LayoutGraph(
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nets={"USB_DP": 1, "USB_DM": 2},
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segments=[
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LayoutSegment(start=(0, 0), end=(10, 0), width=0.2, layer="F.Cu", net="USB_DP"),
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LayoutSegment(start=(0, 1), end=(8, 1), width=0.2, layer="F.Cu", net="USB_DM"),
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],
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)
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inv = build_pcb_inventory(layout)
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names = {n.name: n for n in inv.nets}
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assert names["USB_DP"].length_mm == 10.0
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assert names["USB_DP"].pair == "USB_DM"
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def test_layout_context_includes_via_counts():
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from backend.periscopex.models import LayoutStackup, LayoutVia, LayoutZone
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graph = _graph()
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plan = FunctionalGroupsReport(
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domains=[PlacementDomain(domain_id="3v3", power_nets=["+3V3"], ic_refs=["U3"])],
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groups=[PlacementIcGroup(ref="U3", satellites=[])],
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)
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layout = LayoutGraph(
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stackup=LayoutStackup(
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copper_layers=["F.Cu", "B.Cu"],
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dielectrics=[],
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copper_thickness_mm=0.035,
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),
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footprints={
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"U3": LayoutFootprint(
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reference="U3", x=0, y=0, layer="F.Cu",
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courtyard=[(-2, -2), (2, -2), (2, 2), (-2, 2)],
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pads=[LayoutPad(number="1", x=0, y=0, net="+3V3")],
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),
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},
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vias=[
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LayoutVia(x=0.2, y=0.1, net="GND", drill=0.3),
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LayoutVia(x=-0.4, y=0.0, net="GND", drill=0.3),
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],
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segments=[
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LayoutSegment(start=(0, 0), end=(5, 0), width=0.45, layer="F.Cu", net="+3V3"),
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],
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zones=[
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LayoutZone(
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net="",
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layer="F.Cu",
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keepout=True,
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name="ANT_KEEPOUT",
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outlines=[[(20, 20), (30, 20), (30, 30), (20, 30)]],
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),
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],
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)
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text = build_pcb_layout_context("U3", graph, layout, plan)
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assert "Vias under footprint: 2" in text
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assert "count=2" in text
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assert "0.3 mm" in text
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assert "Copper thickness: 35 µm" in text
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assert "width=0.45 mm" in text
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assert "ANT_KEEPOUT" in text
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assert "Board keepout polygons" in text
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def test_pcb_ai_finding_gets_action():
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from backend.periscopex.finding_engine import complete_finding
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from backend.periscopex.models import Finding
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from backend.services.pcb_validation import _ensure_recs
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f = Finding(
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designator="U1",
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mpn="PADIC",
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finding="PowerPAD under U1",
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why="datasheet thermal pad",
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status="INFO",
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recommendation="",
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action="",
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source="pcb_review",
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)
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_ensure_recs([f])
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complete_finding(f)
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assert f.action.strip()
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assert f.recommendation.strip()
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assert f.finding_class == "REVIEW"
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assert f.facts
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assert f.requirement
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def test_parse_review_action_field_without_recommendation():
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from backend.periscopex.review_parse import parse_submit_review as _parse_review
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result = _parse_review(
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{
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"findings": [{
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"finding": "EPAD vias present",
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"why": "layout note",
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"status": "INFO",
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"source_page": 12,
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"source_quote": "Connect EPAD with vias to GND.",
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"action": "Keep the nine 0.3 mm vias under U5 EPAD.",
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}],
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"checked_areas": ["thermal"],
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},
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"U5",
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"ESP",
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)
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f = result.findings[0]
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assert f.action == "Keep the nine 0.3 mm vias under U5 EPAD."
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assert f.recommendation == "Keep the nine 0.3 mm vias under U5 EPAD."
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def test_layout_context_includes_domain_and_group():
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graph = _graph()
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plan = FunctionalGroupsReport(
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domains=[PlacementDomain(domain_id="3v3", power_nets=["+3V3"], ic_refs=["U3"])],
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groups=[PlacementIcGroup(ref="U3", satellites=[])],
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)
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layout = LayoutGraph(
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footprints={"U3": LayoutFootprint(reference="U3", x=1, y=2, layer="F.Cu")},
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)
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text = build_pcb_layout_context("U3", graph, layout, plan)
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assert "Domain: 3v3" in text
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assert "Functional group: U3" in text
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assert "Footprint U3" in text
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assert "Vias under footprint" in text
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def test_merge_reports_prefixes_do_not_collide():
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schema = {"findings": [{"finding_id": "U3-001", "status": "WARNING"}]}
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pcb = {"findings": [{"finding_id": "PCB-U3-001", "status": "ERROR"}]}
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merged = merge_schema_pcb_reports(schema, pcb)
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ids = [f["finding_id"] for f in merged["findings"]]
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assert ids == ["U3-001", "PCB-U3-001"]
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assert merged["summary"]["ERROR"] == 1
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assert merged["summary"]["WARNING"] == 1
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def test_assign_fills_empty_recommendation():
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from backend.periscopex.models import Finding
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f = Finding(
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designator="U1", mpn="", finding="x", why="y", status="INFO",
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recommendation="",
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)
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assign_pcb_finding_ids([f])
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assert f.finding_id == "PCB-U1-001"
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assert f.recommendation
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def test_pcb_busy_helpers():
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active = frozenset({"queued", "running"})
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analysis = frozenset({STATUS_QUEUED, STATUS_RUNNING})
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draft = ProjectMeta(id="p", name="t", created="2026-01-01", user_id="u")
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assert (draft.pcb_status or "draft") not in active
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draft.pcb_status = "queued"
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assert (draft.pcb_status or "draft") in active
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draft.status = STATUS_RUNNING
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assert draft.status in analysis
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def test_heal_dead_analysis_worker_unblocks_pcb(tmp_path: Path, monkeypatch):
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from backend.services import job_runner, projects as proj_svc
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from backend.services.storage import LocalStorageBackend
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storage = LocalStorageBackend(tmp_path)
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meta = proj_svc.create_project(storage, "usr_jwt", "board")
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proj_svc.update_project(
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storage, "usr_jwt", meta.id,
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status=STATUS_RUNNING,
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has_pcb=True,
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has_bom=True,
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has_netlist=True,
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pcb_status="draft",
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)
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monkeypatch.setattr(job_runner, "get_execution_state", lambda _n: "failed")
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healed = proj_svc.heal_if_pipeline_finished(storage, "usr_jwt", meta.id)
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assert healed is not None
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assert healed.status == "error"
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from backend.services.pcb_pipeline import analysis_busy
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assert not analysis_busy(healed)
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from fastapi.testclient import TestClient
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from backend.main import app
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from backend.services.storage import LocalStorageBackend
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app.state.storage = LocalStorageBackend(tmp_path)
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client = TestClient(app)
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pid = client.post("/api/projects", json={"name": "noboard"}).json()["id"]
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resp = client.post(f"/api/pipeline/{pid}/pcb/start")
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assert resp.status_code == 400
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assert "kicad_pcb" in resp.json()["detail"]
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def test_update_project_writes_storage_prefix_not_stale_user_id(tmp_path: Path):
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"""JWT owner path with JSON still saying user_id=local (live Emmaforo)."""
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from backend.services.storage import LocalStorageBackend
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storage = LocalStorageBackend(tmp_path)
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pid = "759a4dea9612"
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owner = "usr_jwt_owner"
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storage.write_json(
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f"users/{owner}/projects/{pid}/project.json",
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{
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"id": pid,
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"name": "Emmaforo",
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"user_id": "local",
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"created": "2026-01-01T00:00:00Z",
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"status": "complete",
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"has_pcb": True,
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"has_bom": True,
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"has_netlist": True,
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"pcb_status": "draft",
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},
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)
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from backend.services import projects as proj_svc
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proj_svc.update_project(storage, owner, pid, pcb_status="queued")
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jwt_meta = proj_svc.get_project(storage, owner, pid)
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assert jwt_meta is not None
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assert jwt_meta.pcb_status == "queued"
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assert proj_svc.get_project(storage, "local", pid) is None
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def _ldo_graph_layout(*, i_load=10.0, tj_max=150.0, width=0.15, thickness=0.035):
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from backend.periscopex.models import (
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ComponentConstraints,
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LayoutStackup,
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Pin,
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PinConnection,
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SimpleComponentSpecs,
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)
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pins = {"1": "VIN", "2": "VOUT"}
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cons = ComponentConstraints(
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mpn="LDO1",
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pintable=[
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Pin(number="1", name="VIN"),
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Pin(number="2", name="VOUT"),
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],
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absolute_maximum_ratings=[],
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rules=[],
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)
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graph = DesignGraph(
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components={
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"U1": Component(
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reference="U1", value="LDO", footprint="",
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component_type=ComponentType.IC, mpn="LDO1",
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component_subtype="ic.power.ldo",
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pins=pins,
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specs=SimpleComponentSpecs(
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specs_type="discrete",
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values={"i_load_a": i_load, "tj_max": tj_max, "theta_ja": 50},
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),
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),
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},
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nets={
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"VIN": Net(
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name="VIN", net_type=NetType.POWER, voltage=5.0,
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pins=[PinConnection(component_ref="U1", pin_number="1")],
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),
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"VOUT": Net(
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name="VOUT", net_type=NetType.POWER, voltage=3.3,
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pins=[PinConnection(component_ref="U1", pin_number="2")],
|
|
),
|
|
},
|
|
)
|
|
layout = LayoutGraph(
|
|
stackup=LayoutStackup(
|
|
copper_layers=["F.Cu", "B.Cu"],
|
|
dielectrics=[],
|
|
copper_thickness_mm=thickness,
|
|
),
|
|
footprints={
|
|
"U1": LayoutFootprint(
|
|
reference="U1", x=0, y=0, layer="F.Cu",
|
|
courtyard=[(-2, -2), (2, -2), (2, 2), (-2, 2)],
|
|
pads=[LayoutPad(number="2", x=0, y=0, net="VOUT")],
|
|
),
|
|
},
|
|
segments=[
|
|
LayoutSegment(start=(0, 0), end=(20, 0), width=width, layer="F.Cu", net="VOUT"),
|
|
],
|
|
)
|
|
return graph, {"LDO1": cons}, layout
|
|
|
|
|
|
def test_power_trace_ipc2221_errors_when_load_exceeds_ampacity():
|
|
from backend.periscopex.pcb_power_thermal import check_pcb_power_traces
|
|
|
|
graph, cmap, layout = _ldo_graph_layout()
|
|
findings = check_pcb_power_traces(graph, cmap, layout)
|
|
assert findings
|
|
assert findings[0].rule_id == "PE-PWR-001"
|
|
assert findings[0].status == "ERROR"
|
|
assert "IPC-2221" in findings[0].finding
|
|
assert findings[0].recommendation
|
|
|
|
|
|
def test_power_trace_uses_parsed_width_and_thickness():
|
|
from backend.periscopex.pcb_power_thermal import check_pcb_power_traces
|
|
|
|
graph, cmap, layout = _ldo_graph_layout(i_load=0.05, width=1.0, thickness=0.035)
|
|
findings = check_pcb_power_traces(graph, cmap, layout)
|
|
assert findings == []
|
|
|
|
|
|
def test_power_trace_skips_without_i_load():
|
|
from backend.periscopex.pcb_power_thermal import check_pcb_power_traces
|
|
|
|
graph, cmap, layout = _ldo_graph_layout(i_load=10)
|
|
graph.components["U1"].specs.values["i_load_a"] = None # type: ignore[union-attr]
|
|
graph.components["U1"].specs = None
|
|
assert check_pcb_power_traces(graph, cmap, layout) == []
|
|
|
|
|
|
def test_kelvin_sense_pin_on_shared_net():
|
|
from backend.periscopex.models import ComponentConstraints, Pin, PinConnection
|
|
from backend.periscopex.pcb_power_thermal import check_pcb_kelvin
|
|
|
|
cons = ComponentConstraints(
|
|
mpn="AMP",
|
|
pintable=[Pin(number="4", name="ISNS", description="current sense")],
|
|
absolute_maximum_ratings=[],
|
|
rules=[],
|
|
)
|
|
graph = DesignGraph(
|
|
components={
|
|
"U2": Component(
|
|
reference="U2", value="", footprint="",
|
|
component_type=ComponentType.IC, mpn="AMP",
|
|
pins={"4": "ISNS_NET"},
|
|
),
|
|
"R1": Component(
|
|
reference="R1", value="10m", footprint="",
|
|
component_type=ComponentType.RESISTOR, mpn="",
|
|
pins={"1": "ISNS_NET", "2": "GND"},
|
|
),
|
|
"U9": Component(
|
|
reference="U9", value="", footprint="",
|
|
component_type=ComponentType.IC, mpn="LOAD",
|
|
pins={"1": "ISNS_NET"},
|
|
),
|
|
},
|
|
nets={
|
|
"ISNS_NET": Net(
|
|
name="ISNS_NET", net_type=NetType.SIGNAL,
|
|
pins=[
|
|
PinConnection(component_ref="U2", pin_number="4"),
|
|
PinConnection(component_ref="R1", pin_number="1"),
|
|
PinConnection(component_ref="U9", pin_number="1"),
|
|
],
|
|
),
|
|
},
|
|
)
|
|
findings = check_pcb_kelvin(graph, {"AMP": cons})
|
|
assert findings and findings[0].rule_id == "PE-KEL-001"
|
|
assert findings[0].status == "WARNING"
|
|
|
|
|
|
def test_pcb_ai_skips_without_library_extraction():
|
|
import asyncio
|
|
from backend.services.pcb_validation import review_pcb_ics
|
|
|
|
graph = DesignGraph(
|
|
components={
|
|
"U1": Component(
|
|
reference="U1", value="X", footprint="",
|
|
component_type=ComponentType.IC, mpn="NOEXT",
|
|
pins={"1": "GND"},
|
|
),
|
|
},
|
|
nets={},
|
|
)
|
|
|
|
async def _run():
|
|
return await review_pcb_ics(
|
|
graph, {}, None, None, None, Path("/tmp"),
|
|
)
|
|
|
|
_f, _c, skipped = asyncio.run(_run())
|
|
assert skipped
|
|
assert "library extraction" in skipped[0]["reason"]
|
|
|
|
|
|
def test_library_constraints_fill_from_storage(tmp_path: Path):
|
|
from backend.periscopex.models import ComponentConstraints, Pin
|
|
from backend.services.pcb_pipeline import _load_constraints_map
|
|
from backend.services.storage import LocalStorageBackend
|
|
|
|
storage = LocalStorageBackend(tmp_path)
|
|
cons = ComponentConstraints(
|
|
mpn="LIBIC",
|
|
pintable=[Pin(number="1", name="VCC")],
|
|
absolute_maximum_ratings=[],
|
|
rules=[],
|
|
)
|
|
storage.write_json("library/extracted/LIBIC.json", cons.model_dump())
|
|
cmap = _load_constraints_map(tmp_path / "missing", storage)
|
|
assert "LIBIC" in cmap
|
|
assert cmap["LIBIC"].pintable[0].name == "VCC"
|
|
|
|
|
|
def test_thermal_copper_warns_without_pour_or_vias():
|
|
from backend.periscopex.pcb_power_thermal import check_pcb_thermal_copper
|
|
|
|
graph, cmap, layout = _ldo_graph_layout(i_load=0.5, width=1.0)
|
|
findings = check_pcb_thermal_copper(graph, cmap, layout)
|
|
assert findings
|
|
assert findings[0].rule_id == "PE-THM-001"
|
|
assert findings[0].status == "WARNING"
|
|
assert findings[0].recommendation
|
|
|
|
|
|
def test_gnd_stitch_skips_tiny_gpio():
|
|
from backend.periscopex.models import LayoutZone, PinConnection
|
|
from backend.periscopex.pcb_power_thermal import check_pcb_gnd_stitch
|
|
|
|
graph = DesignGraph(
|
|
components={
|
|
"U1": Component(
|
|
reference="U1", value="", footprint="",
|
|
component_type=ComponentType.IC, mpn="X",
|
|
pins={"1": "GPIO4"},
|
|
),
|
|
},
|
|
nets={
|
|
"GPIO4": Net(
|
|
name="GPIO4", net_type=NetType.SIGNAL,
|
|
pins=[PinConnection(component_ref="U1", pin_number="1")],
|
|
),
|
|
},
|
|
)
|
|
layout = LayoutGraph(
|
|
footprints={},
|
|
segments=[
|
|
LayoutSegment(start=(0, 0), end=(0.1, 3), width=0.2, layer="F.Cu", net="GPIO4"),
|
|
],
|
|
zones=[
|
|
LayoutZone(net="GND", layer="B.Cu", outlines=[[(0, -5), (20, -5), (20, 5), (0, 5)]]),
|
|
],
|
|
vias=[],
|
|
)
|
|
assert check_pcb_gnd_stitch(graph, layout) == []
|
|
|
|
|
|
def test_gnd_stitch_info_when_signal_has_pour_but_no_via():
|
|
from backend.periscopex.models import LayoutVia, LayoutZone, PinConnection
|
|
from backend.periscopex.pcb_power_thermal import check_pcb_gnd_stitch
|
|
|
|
graph = DesignGraph(
|
|
components={
|
|
"U1": Component(
|
|
reference="U1", value="", footprint="",
|
|
component_type=ComponentType.IC, mpn="X",
|
|
pins={"1": "USB_DP"},
|
|
),
|
|
},
|
|
nets={
|
|
"USB_DP": Net(
|
|
name="USB_DP", net_type=NetType.SIGNAL,
|
|
pins=[PinConnection(component_ref="U1", pin_number="1")],
|
|
),
|
|
},
|
|
)
|
|
layout = LayoutGraph(
|
|
footprints={},
|
|
segments=[
|
|
LayoutSegment(start=(0, 0), end=(20, 8), width=0.2, layer="F.Cu", net="USB_DP"),
|
|
],
|
|
zones=[
|
|
LayoutZone(net="GND", layer="B.Cu", outlines=[[(0, -5), (20, -5), (20, 10), (0, 10)]]),
|
|
],
|
|
vias=[],
|
|
)
|
|
findings = check_pcb_gnd_stitch(graph, layout)
|
|
assert findings and findings[0].rule_id == "PE-STCH-001"
|
|
assert findings[0].status == "INFO"
|
|
assert findings[0].action
|
|
layout.vias = [LayoutVia(x=10, y=4, net="GND", drill=0.3)]
|
|
assert check_pcb_gnd_stitch(graph, layout) == []
|
|
|
|
|
|
def test_pcb_pipeline_imports_build_placement_plan():
|
|
import backend.services.pcb_pipeline as pcb_pipeline
|
|
from backend.periscopex.functional_groups import build_placement_plan as expected
|
|
|
|
assert pcb_pipeline.build_placement_plan is expected
|
|
|