michele
866c2e9242
L3 CHANNEL structure for timing budget, insertion loss, return loss, crosstalk, and complete channel. Numeric PASS/FAIL only from existing channel FACT; otherwise a visible skip. No OpenEMS, no invented S-parameters, no M6 packs.
262 lines
8.6 KiB
Python
262 lines
8.6 KiB
Python
"""M4 L2 ELECTRICAL certifier: Z from cite/datasheet/stackup only; never 90 Ω folklore."""
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from __future__ import annotations
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import json
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from backend.periscopex.models import (
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Component,
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ComponentConstraints,
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ComponentType,
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DesignGraph,
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LayoutGraph,
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Net,
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NetType,
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PinConnection,
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)
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from backend.periscopex.protocol_catalog import (
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ConstraintSource,
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PhysicalInterface,
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ProtocolConstraint,
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)
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from backend.periscopex.protocol_l0 import protocol_exam
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from backend.periscopex.protocol_l2 import (
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_pack,
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certify_instance_l2,
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certify_l2,
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electrical_verdict,
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intersect_windows,
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)
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from backend.periscopex.protocol_recognize import recognize_physical_buses
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def _ic(ref: str, pins: dict[str, str], *, mpn: str = "", value: str = "") -> Component:
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return Component(
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reference=ref, value=value or mpn, footprint="",
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component_type=ComponentType.IC, mpn=mpn or None, pins=pins,
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)
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def _net(name: str, *pairs: tuple[str, str]) -> Net:
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return Net(
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name=name, net_type=NetType.SIGNAL,
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pins=[PinConnection(component_ref=r, pin_number=p) for r, p in pairs],
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)
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def _usb_connected() -> DesignGraph:
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return DesignGraph(
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components={
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"U1": _ic("U1", {"1": "USB_D+", "2": "USB_D-"}, mpn="CH340E"),
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"J2": Component(
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reference="J2", value="USB2_TypeA",
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footprint="USB_A",
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component_type=ComponentType.CONNECTOR,
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pins={"2": "USB_D+", "3": "USB_D-"},
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),
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},
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nets={
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"USB_D+": _net("USB_D+", ("U1", "1"), ("J2", "2")),
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"USB_D-": _net("USB_D-", ("U1", "2"), ("J2", "3")),
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},
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)
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def _axi_graph() -> DesignGraph:
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return DesignGraph(
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components={
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"U3": _ic("U3", {"1": "AXI_AWVALID"}, mpn="XC7A100T", value="AXI4 interconnect"),
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},
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nets={"AXI_AWVALID": _net("AXI_AWVALID", ("U3", "1"))},
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)
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def _ddr_graph() -> DesignGraph:
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pins = {str(i): f"DDR4_DQ{i}" for i in range(8)}
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pins.update({"8": "DDR4_DQS0_P", "9": "DDR4_DQS0_N"})
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u_mem = _ic("U5", pins, mpn="MT41K256M16TW", value="DDR4")
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u_cpu = _ic("U4", {str(i): pins[str(i)] for i in pins}, mpn="STM32", value="MCU")
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nets = {n: _net(n, ("U5", p), ("U4", p)) for p, n in pins.items()}
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return DesignGraph(components={"U5": u_mem, "U4": u_cpu}, nets=nets)
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def _cons(mpn: str, rules: list[dict]) -> ComponentConstraints:
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return ComponentConstraints(
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mpn=mpn, pintable=[], absolute_maximum_ratings=[], rules=[],
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layout_rules=rules,
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)
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def _l2_for(graph: DesignGraph, logical_sub: str, **kwargs):
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insts = recognize_physical_buses(graph)
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by, findings = certify_l2(graph, insts, **kwargs)
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rows = []
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for inst in insts:
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if logical_sub in inst.logical_protocol_id:
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rows.extend(by.get(inst.instance_id, []))
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return rows, findings, insts
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def _cite() -> ConstraintSource:
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return ConstraintSource(document="USB 2.0 spec", organization="USB-IF", section="7.1.1")
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def test_usb_z_missing_source_never_invents_90():
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zrep = {"nets": [
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{"net_name": "USB_D+", "z0_avg_ohms": 45.0},
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{"net_name": "USB_D-", "z0_avg_ohms": 46.0},
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]}
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rows, findings, _ = _l2_for(_usb_connected(), "usb2", impedance_nets=zrep)
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z = [r for r in rows if r.check == "differential_impedance"]
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assert z
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assert z[0].result in {"MISSING_SOURCE", "UNKNOWN"}
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assert z[0].result != "PASS"
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blob = json.dumps(z[0].model_dump())
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assert "90" not in blob
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assert any(f.rule_id == "PE-PRT-L2-001" for f in findings)
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assert any("non certificata a L2" in (f.finding or "") for f in findings)
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def test_usb_z_skip_when_no_stackup_measurement():
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rows, findings, _ = _l2_for(_usb_connected(), "usb2")
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z = [r for r in rows if r.check == "differential_impedance"]
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assert z
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assert z[0].result in {"MISSING_SOURCE", "UNKNOWN"}
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assert z[0].measured_ohm is None
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assert any("mancanza di Z" in (f.finding or "") for f in findings)
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def test_cited_pack_z_pass_and_fail():
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graph = _usb_connected()
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insts = recognize_physical_buses(graph)
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usb = [i for i in insts if "usb" in i.logical_protocol_id][0]
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iface = PhysicalInterface(
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id="usb2-hs-dpair",
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logical_protocol_id="usb2-hs",
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bus_type="SERIAL",
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physical_layer="SERIAL_DIFFERENTIAL",
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pcb_relevant="YES",
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required_checks=["differential_impedance"],
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constraints=[ProtocolConstraint(
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id="usb-z",
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parameter="differential_impedance",
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value_kind="NUMERIC",
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mandatory="MANDATORY",
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source_type="STANDARD",
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source_class="NORMATIVE",
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value=90.0,
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unit="ohm",
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source=_cite(),
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limit_kind="STANDARD",
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)],
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)
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zrep = {"nets": [{"net_name": "USB_D+", "zdiff_ohm": 90.0}]}
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ok = certify_instance_l2(graph, usb, iface, impedance_nets=zrep)
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assert ok[0].result == "PASS"
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assert ok[0].measured_ohm == 90.0
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bad = certify_instance_l2(
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graph, usb, iface,
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impedance_nets={"nets": [{"net_name": "USB_D+", "zdiff_ohm": 40.0}]},
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)
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assert bad[0].result == "FAIL"
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def test_silicon_cross_phy_subset():
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assert intersect_windows([(80.0, 100.0), (85.0, 95.0)]) == (85.0, 95.0)
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graph = _usb_connected()
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cmap = {
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"CH340E": _cons("CH340E", [{
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"kind": "impedance",
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"z_min_ohm": 80,
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"z_max_ohm": 100,
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"note": "CH340E USB",
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"source_page": 12,
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}]),
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}
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# second PHY on the same nets
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extra = _ic("U9", {"1": "USB_D+", "2": "USB_D-"}, mpn="USBPHY1")
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graph.components["U9"] = extra
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cmap["USBPHY1"] = _cons("USBPHY1", [{
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"kind": "zdiff",
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"z_min_ohm": 85,
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"z_max_ohm": 95,
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"note": "PHY subset",
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"source_page": 3,
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}])
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zrep = {"nets": [{"net_name": "USB_D+", "zdiff_ohm": 90.0}]}
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rows, _, _ = _l2_for(graph, "usb2", constraints_map=cmap, impedance_nets=zrep)
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z = [r for r in rows if r.check == "differential_impedance"]
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assert z
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assert z[0].result == "PASS"
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assert z[0].limit_ohm_min == 85.0
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assert z[0].limit_ohm_max == 95.0
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zrep_lo = {"nets": [{"net_name": "USB_D+", "zdiff_ohm": 70.0}]}
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rows_lo, findings, _ = _l2_for(
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graph, "usb2", constraints_map=cmap, impedance_nets=zrep_lo,
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)
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zlo = [r for r in rows_lo if r.check == "differential_impedance"]
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assert zlo[0].result == "FAIL"
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assert any(f.rule_id == "PE-PRT-L2-002" for f in findings)
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def test_axi_internal_l2_not_applicable():
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rows, _, _ = _l2_for(_axi_graph(), "axi4")
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assert rows
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assert all(r.result == "NOT_APPLICABLE" for r in rows)
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sec, findings = protocol_exam(_axi_graph())
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assert sec.max_level_reached == "L3"
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assert sec.macrophase == "M9"
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assert all(f.status != "ERROR" for f in findings)
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blob = json.dumps([r.model_dump() for r in rows])
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assert "L0/L1 are not electrical" in blob
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def test_ddr_impedance_phy_dependent_not_invented_ohm():
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rows, findings, _ = _l2_for(_ddr_graph(), "ddr4")
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z = [r for r in rows if r.check == "impedance"]
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assert z
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assert z[0].result in {"PHY_DEPENDENT", "UNKNOWN", "VENDOR_DEPENDENT"}
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assert z[0].result != "PASS"
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blob = json.dumps(z[0].model_dump())
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assert "40" not in blob
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assert "90" not in blob
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assert any(f.rule_id == "PE-PRT-L2-001" for f in findings)
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def test_length_is_not_delay_timing_unknown():
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cons = ProtocolConstraint(
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id="t",
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parameter="timing",
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value_kind="NUMERIC",
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mandatory="MANDATORY",
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source_type="STANDARD",
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source_class="NORMATIVE",
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value=100.0,
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unit="ps",
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source=_cite(),
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)
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assert electrical_verdict(cons, 12.0, None) == "UNKNOWN"
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def test_recommended_never_fail_l2():
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rec = _pack("return_path", "FAIL", "RECOMMENDED", notes="weak")
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assert rec.result != "FAIL"
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assert rec.status != "ERROR"
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def test_l2_does_not_run_l3_or_geometry():
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rows, _, _ = _l2_for(_usb_connected(), "usb2")
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assert not any(r.check in {"insertion_loss", "return_loss", "length", "intra_pair_skew"} for r in rows)
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blob = json.dumps([r.model_dump() for r in rows])
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assert "openems" not in blob.lower()
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def test_protocol_exam_attaches_l2_checks():
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sec, _ = protocol_exam(_usb_connected())
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assert sec.max_level_reached == "L3"
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row = sec.recognized_instances[0]
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assert row.get("l2_checks")
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assert all(c.get("level") == "L2" for c in row["l2_checks"])
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assert row.get("l1_checks") is not None
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assert row.get("l0_checks") is not None
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