michele
c87adf11a9
Trigger λ/10 and tr/(6 tpd) from FACT; pairs analyzed together; Z only from datasheet; visible INSUFFICIENT skips; lossless RLGC cascade (no OpenEMS).
241 lines
8.3 KiB
Python
241 lines
8.3 KiB
Python
"""AF trace v1: trigger, visible skips, pair-together, no invented ohms."""
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from __future__ import annotations
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from pathlib import Path
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import pytest
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from backend.periscopex.af_rlgc import cascade_sparam
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from backend.periscopex.af_trace_check import check_af_traces
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from backend.periscopex.af_trigger import evaluate_trigger, iter_af_units
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from backend.periscopex.finding_engine import lookup_rule
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from backend.periscopex.models import (
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Component,
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ComponentConstraints,
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ComponentType,
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DesignGraph,
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LayoutDielectric,
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LayoutFootprint,
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LayoutGraph,
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LayoutPad,
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LayoutSegment,
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LayoutStackup,
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LayoutVia,
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Net,
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NetType,
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Pin,
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PinConnection,
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)
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from backend.periscopex.pcb_checks import run_pcb_checks
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from backend.periscopex.parsers_kicad_pcb import parse_kicad_pcb
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_HUB = Path("/Users/michelebigi/Development/HubAudio/hardware/kicad/HubAudio/HubAudio.kicad_pcb")
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def _ic(ref: str, pins: dict[str, str], *, mpn: str = "PHY") -> Component:
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return Component(
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reference=ref, value=mpn, footprint="",
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component_type=ComponentType.IC, mpn=mpn, pins=pins,
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)
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def _net(name: str, *pairs: tuple[str, str]) -> Net:
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return Net(
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name=name, net_type=NetType.SIGNAL,
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pins=[PinConnection(component_ref=r, pin_number=p) for r, p in pairs],
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)
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def _usb_graph() -> DesignGraph:
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return DesignGraph(
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components={
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"U1": _ic("U1", {"1": "USB_D+", "2": "USB_D-"}),
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"J2": Component(
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reference="J2", value="USB_C", footprint="",
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component_type=ComponentType.CONNECTOR,
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pins={"A6": "USB_D+", "A7": "USB_D-"},
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),
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},
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nets={
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"USB_D+": _net("USB_D+", ("U1", "1"), ("J2", "A6")),
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"USB_D-": _net("USB_D-", ("U1", "2"), ("J2", "A7")),
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},
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)
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def _stack() -> LayoutStackup:
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return LayoutStackup(
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copper_layers=["F.Cu", "B.Cu"],
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dielectrics=[LayoutDielectric(name="core", er=4.5, height_mm=0.15)],
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copper_thickness_mm=0.035,
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)
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def _pair_layout(*, length: float = 10.0, elbow: bool = False) -> LayoutGraph:
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segs = [
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LayoutSegment(start=(0, 0), end=(length, 0), width=0.2, layer="F.Cu", net="USB_D+"),
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LayoutSegment(start=(0, 0.4), end=(length, 0.4), width=0.2, layer="F.Cu", net="USB_D-"),
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]
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if elbow:
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segs.append(LayoutSegment(
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start=(length, 0), end=(length, 3), width=0.2, layer="F.Cu", net="USB_D+",
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))
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return LayoutGraph(
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footprints={
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"U1": LayoutFootprint(
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reference="U1", footprint="P", x=0, y=0,
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pads=[LayoutPad(number="1", x=0, y=0, net="USB_D+"),
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LayoutPad(number="2", x=0, y=0.4, net="USB_D-")],
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),
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"J2": LayoutFootprint(
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reference="J2", footprint="P", x=length, y=0,
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pads=[LayoutPad(number="A6", x=length, y=0, net="USB_D+"),
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LayoutPad(number="A7", x=length, y=0.4, net="USB_D-")],
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),
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},
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segments=segs,
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stackup=_stack(),
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)
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def _rules(*extra: dict) -> dict:
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rules = list(extra)
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return {
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"PHY": ComponentConstraints(
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mpn="PHY", pintable=[Pin(number="1", name="D+")],
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absolute_maximum_ratings=[], rules=[],
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layout_rules=rules,
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),
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}
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def test_catalog_pe_af_ids():
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for rid in ("PE-AF-001", "PE-AF-002", "PE-AF-020", "PE-AF-050", "PE-AF-060"):
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rec = lookup_rule(rid)
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assert rec is not None, rid
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assert rec.domain == "pcb"
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def test_pair_is_one_unit():
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units = iter_af_units(_pair_layout(), _usb_graph())
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assert len(units) == 1
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assert set(units[0].nets) == {"USB_D+", "USB_D-"}
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def test_gpio_is_not_a_candidate():
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g = DesignGraph(
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components={"U1": _ic("U1", {"1": "SDA"})},
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nets={"SDA": _net("SDA", ("U1", "1"))},
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)
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layout = LayoutGraph(
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segments=[LayoutSegment(start=(0, 0), end=(80, 0), width=0.2, layer="F.Cu", net="SDA")],
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stackup=_stack(),
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)
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assert check_af_traces(g, {}, layout) == []
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def test_missing_tr_f_is_visible_skip_no_ohm():
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layout = _pair_layout()
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out = check_af_traces(_usb_graph(), {}, layout)
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assert out
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assert all(f.rule_id == "PE-AF-002" for f in out)
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assert len(out) == 1
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text = out[0].finding
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assert "Pista ad alta frequenza non controllata per mancanza di" in text
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assert "tr" in text and "f" in text
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assert out[0].evidence_status == "INSUFFICIENT"
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assert out[0].finding_class == "REVIEW"
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blob = (out[0].finding + out[0].facts).lower()
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assert "90" not in blob and "50" not in blob and "ω" not in blob and "ohm" not in blob
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def test_short_pair_with_tr_is_not_af():
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cons = _rules({"kind": "rise_time", "net_class": "usb2", "tr_ns": 5.0})
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layout = _pair_layout(length=8.0)
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trig = evaluate_trigger(_usb_graph(), cons, layout, iter_af_units(layout, _usb_graph())[0])
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assert trig.af is False
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assert check_af_traces(_usb_graph(), cons, layout) == []
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def test_triggered_without_z_target_is_visible_skip():
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cons = _rules({"kind": "rise_time", "net_class": "usb2", "tr_ns": 0.05})
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layout = _pair_layout(length=40.0)
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out = check_af_traces(_usb_graph(), cons, layout)
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skips = [f for f in out if f.rule_id == "PE-AF-002"]
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assert skips
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assert "Z target datasheet" in skips[0].finding
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assert all("90" not in f.finding for f in out)
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def test_triggered_zdiff_window_uses_datasheet_not_folklore():
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cons = _rules(
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{"kind": "rise_time", "net_class": "usb2", "tr_ns": 0.05},
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{"kind": "impedance", "net_class": "usb2", "zdiff_ohm": 90, "tolerance_pct": 10},
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)
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layout = _pair_layout(length=40.0)
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out = check_af_traces(_usb_graph(), cons, layout)
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zhits = [f for f in out if f.rule_id == "PE-AF-050"]
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if zhits:
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assert zhits[0].net in {"USB_D+", "USB_D-"}
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assert "90" in zhits[0].finding or "90" in zhits[0].facts
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assert zhits[0].calculation == "" or "Z_ref" in zhits[0].calculation
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assert sum(1 for f in out if f.rule_id == "PE-AF-050") <= 1
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def test_right_angle_on_triggered_pair():
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cons = _rules({"kind": "rise_time", "net_class": "usb2", "tr_ns": 0.05})
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layout = _pair_layout(length=40.0, elbow=True)
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out = check_af_traces(_usb_graph(), cons, layout)
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assert any(f.rule_id == "PE-AF-020" for f in out)
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def test_via_without_span_is_visible_skip():
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cons = _rules({"kind": "rise_time", "net_class": "usb2", "tr_ns": 0.05})
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layout = _pair_layout(length=40.0)
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layout.vias = [LayoutVia(x=5, y=0, net="USB_D+", drill=0.3)]
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out = check_af_traces(_usb_graph(), cons, layout)
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assert any("span via" in f.finding for f in out if f.rule_id == "PE-AF-002")
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def test_via_with_span_is_not_a_pad():
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cons = _rules({"kind": "rise_time", "net_class": "usb2", "tr_ns": 0.05})
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layout = _pair_layout(length=40.0)
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layout.vias = [LayoutVia(x=5, y=0, net="USB_D+", drill=0.3, layers=("F.Cu", "B.Cu"))]
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out = check_af_traces(_usb_graph(), cons, layout)
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assert any(f.rule_id == "PE-AF-060" for f in out)
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assert all(f.rule_id != "PE-VIA-001" for f in out)
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def test_si_stub_still_fires_without_af_module():
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layout = _pair_layout(length=10.0, elbow=True)
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cons = _rules({"kind": "stub", "net_class": "usb2", "max_distance_mm": 1.0, "note": "USB stub"})
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pcb = run_pcb_checks(_usb_graph(), cons, layout)
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assert any(f.rule_id == "PE-SI-007" for f in pcb)
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def test_cascade_needs_positive_zref():
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assert cascade_sparam([50.0], [0.04], 3.5, 1e9, 0.0) is None
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r = cascade_sparam([50.0], [0.04], 3.5, 1e9, 50.0)
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assert r is not None
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assert r.n_sections == 1
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@pytest.mark.skipif(not _HUB.is_file(), reason="HubAudio board not on this machine")
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def test_hubaudio_usb_skip_has_no_invented_ohm():
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layout = parse_kicad_pcb(_HUB)
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graph = DesignGraph(
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components={"U1": _ic("U1", {"1": "USB_D+", "2": "USB_D-"})},
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nets={
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"USB_D+": _net("USB_D+", ("U1", "1")),
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"USB_D-": _net("USB_D-", ("U1", "2")),
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},
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)
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# Real net names may be hierarchical; still must not invent ohms on AF skips.
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out = check_af_traces(graph, {}, layout)
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for f in out:
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if f.rule_id == "PE-AF-002":
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low = f.finding.lower()
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assert "90 Ω" not in f.finding and "50 Ω" not in f.finding
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assert "90 ohm" not in low
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