michele
facbaa2305
Layout and AI findings always get action (fallback recommendation). The card renders that sentence in the body. PCB review context now includes vias under the footprint, copper thickness, nearby widths, courtyard, and keepout polygons.
319 lines
12 KiB
Python
319 lines
12 KiB
Python
"""PCB datasheet review prompt and layout neighborhood context (no auto-place)."""
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from __future__ import annotations
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import math
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from collections import defaultdict
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from backend.periscopex.functional_groups import FunctionalGroupsReport
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from backend.periscopex.models import ComponentConstraints, DesignGraph, LayoutGraph
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from backend.periscopex.pcb_inventory import PcbInventoryReport
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from backend.periscopex.pcb_net_match import kicad_nets_match
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from backend.periscopex.pcb_power_thermal import _footprint_region
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from backend.periscopex.placement_check import _in_poly
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from backend.periscopex.si_check import net_length_mm
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PCB_SYSTEM_PROMPT = """\
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You are an electrical engineer reviewing a PCB layout against the IC \
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datasheet knowledge already stored in the shared library extraction \
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(library/extracted). Do NOT re-read or request the PDF — schematic review \
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already did the deep datasheet exam once.
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This is an EXAM of the existing board — do not propose a new floorplan, \
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do not invent millimetres, and do not write Gerbers.
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### Coverage checklist (layout-only)
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- Use pintable, layout_rules, and abs-max from the library JSON in context.
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- Domains and functional groups (IC + satellites).
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- Placement vs numeric layout_rules (max_distance_mm, same_layer, thermal vias).
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- Routing: lengths, skew, stubs — length match only with datasheet millimetres.
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- Power copper: use the parsed copper thickness and nearby trace widths in \
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the "Parsed board geometry" block. Never assume 1 oz or 50 Ω.
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- Thermal: use vias-under-footprint counts and drill sizes vs PowerPAD/EPAD \
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notes. Do not claim the via count or size is missing if that block lists them.
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- Keepout / courtyard: use parsed courtyard vertices and keepout polygons. \
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Do not claim antenna keepout geometry is missing if keepout zones are listed.
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- Kelvin/sense pins, crystal keepout — only if named in the pintable/layout_rules.
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- Creepage/clearance only if the extraction or IEC number is in context.
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### Evidence
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Cite numbers from "Parsed board geometry". Say insufficient evidence ONLY \
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when that extract is empty or explicitly "(none)". If vias, copper thickness, \
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trace widths, or keepout polygons are listed, you MUST use them.
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### Findings
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This is a **design review** of geometry vs the library JSON, not a second \
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datasheet exam. Put board measurements in `finding` (FACT), library text in \
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`why` (REQUIREMENT). Recommended layout notes are never ERROR.
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Every finding MUST have status ERROR, WARNING, or INFO and a non-empty \
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`recommendation` (the Action the designer should take) even for INFO. \
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Call submit_review. Empty findings with checked_areas is valid when the \
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layout matches the extraction.
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"""
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def format_library_extraction(cons: ComponentConstraints) -> str:
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"""Compact shared-library dump so PCB review does not re-ingest the PDF."""
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lines = [
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"### Shared library extraction (library/extracted — do not re-read PDF)",
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f"MPN: {cons.mpn}",
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f"subtype: {cons.component_subtype or '—'}",
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f"model_version: {cons.model_version}",
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]
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if cons.package_info:
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lines.append(
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f"package: {cons.package_info.package} "
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f"({cons.package_info.pin_count} pins)"
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)
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if cons.layout_rules:
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lines.append("layout_rules:")
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for rule in cons.layout_rules[:40]:
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lines.append(f" {rule}")
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if cons.absolute_maximum_ratings:
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lines.append("absolute_maximum_ratings:")
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for r in cons.absolute_maximum_ratings[:30]:
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lines.append(
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f" {r.parameter}: min={r.min} max={r.max} {r.unit} (p.{r.source_page})"
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)
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if cons.pintable:
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lines.append("pintable (number name):")
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for p in cons.pintable[:80]:
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lines.append(f" {p.number} {p.name}")
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return "\n".join(lines)
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def _outline_overlaps_region(
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outlines: list[list[tuple[float, float]]],
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region: list[tuple[float, float]],
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) -> bool:
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if len(region) < 3:
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return False
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rx = [p[0] for p in region]
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ry = [p[1] for p in region]
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cx = (min(rx) + max(rx)) / 2
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cy = (min(ry) + max(ry)) / 2
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for outline in outlines:
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if len(outline) < 3:
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continue
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for x, y in outline:
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if _in_poly(x, y, region):
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return True
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if _in_poly(cx, cy, outline):
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return True
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ox = [p[0] for p in outline]
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oy = [p[1] for p in outline]
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if _in_poly((min(ox) + max(ox)) / 2, (min(oy) + max(oy)) / 2, region):
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return True
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return False
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def format_pcb_geometry(
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ic_ref: str,
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graph: DesignGraph,
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layout: LayoutGraph,
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) -> str:
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"""Vias under footprint, copper thickness, nearby widths, courtyard/keepout."""
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lines = ["### Parsed board geometry (from .kicad_pcb — cite these numbers)"]
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fp = layout.footprints.get(ic_ref)
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if fp is None:
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lines.append(f"Footprint {ic_ref}: (none)")
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lines.append("Vias under footprint: (none)")
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return "\n".join(lines)
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region = _footprint_region(fp)
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if fp.courtyard and len(fp.courtyard) >= 3:
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verts = "; ".join(f"({x:.2f},{y:.2f})" for x, y in fp.courtyard[:16])
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lines.append(f"Courtyard vertices: {verts}")
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else:
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lines.append(
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"Courtyard: (none in .kicad_pcb; using pad bbox + 1.5 mm for via/trace queries)"
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)
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by_net: dict[str, list] = defaultdict(list)
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for v in layout.vias:
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if _in_poly(v.x, v.y, region):
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by_net[v.net or "(unnamed)"].append(v)
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total = sum(len(vs) for vs in by_net.values())
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if total == 0:
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lines.append(
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f"Vias under footprint: 0 (board vias parsed: {len(layout.vias)})"
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)
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else:
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lines.append(
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f"Vias under footprint: {total} (board vias parsed: {len(layout.vias)})"
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)
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for net, vs in sorted(by_net.items(), key=lambda kv: (-len(kv[1]), kv[0])):
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drills = sorted({d for d in (v.drill for v in vs) if d})
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drill_s = (
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", ".join(f"{d:g} mm" for d in drills[:6]) if drills else "(drill not in file)"
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)
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lines.append(f" {net}: count={len(vs)} drill={drill_s}")
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t = layout.stackup.copper_thickness_mm if layout.stackup else None
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if t and t > 0:
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lines.append(f"Copper thickness: {t * 1000:g} µm ({t:g} mm) — parsed stackup, not 1 oz")
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if layout.stackup.copper_layers:
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lines.append("Copper layers: " + ", ".join(layout.stackup.copper_layers[:12]))
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else:
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lines.append("Copper thickness: (none in parsed stackup)")
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pin_nets: set[str] = set()
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comp = graph.components.get(ic_ref)
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if comp:
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pin_nets.update(n for n in comp.pins.values() if n)
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pin_nets.update(p.net for p in fp.pads if p.net)
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widths: list[str] = []
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seen_w: set[tuple[str, float, str]] = set()
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for s in layout.segments:
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if s.width <= 0:
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continue
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near = (
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_in_poly(s.start[0], s.start[1], region)
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or _in_poly(s.end[0], s.end[1], region)
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or _in_poly(
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(s.start[0] + s.end[0]) / 2,
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(s.start[1] + s.end[1]) / 2,
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region,
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)
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)
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on_pin = bool(s.net) and any(kicad_nets_match(s.net, n) for n in pin_nets)
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if not near and not on_pin:
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continue
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key = (s.net or "", round(s.width, 4), s.layer or "")
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if key in seen_w:
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continue
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seen_w.add(key)
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where = "courtyard" if near else "pin-net"
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widths.append(
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f" {s.net or '(unnamed)'} width={s.width:g} mm layer={s.layer or '—'} ({where})"
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)
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if len(widths) >= 24:
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break
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if widths:
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lines.append("Nearby / pin-net trace widths:")
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lines.extend(widths)
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else:
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lines.append("Nearby / pin-net trace widths: (none)")
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keep_hits: list[str] = []
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keep_board: list[str] = []
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for z in layout.zones:
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bbox = ""
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if z.outlines and z.outlines[0]:
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xs = [p[0] for p in z.outlines[0]]
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ys = [p[1] for p in z.outlines[0]]
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bbox = f" bbox=({min(xs):.1f},{min(ys):.1f})-({max(xs):.1f},{max(ys):.1f})"
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label = z.name or z.net or "(unnamed)"
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kind = "keepout" if z.keepout else "zone"
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entry = f" {kind} {label} layer={z.layer or '—'} net={z.net or '—'}{bbox}"
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if z.keepout:
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keep_board.append(entry)
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if _outline_overlaps_region(z.outlines, region):
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keep_hits.append(entry)
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if keep_hits:
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lines.append("Zones overlapping courtyard:")
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lines.extend(keep_hits[:16])
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else:
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lines.append("Zones overlapping courtyard: (none)")
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if keep_board:
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lines.append("Board keepout polygons (antenna / RF):")
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lines.extend(keep_board[:16])
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else:
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lines.append("Board keepout polygons: (none)")
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return "\n".join(lines)
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def build_pcb_layout_context(
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ic_ref: str,
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graph: DesignGraph,
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layout: LayoutGraph | None,
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plan: FunctionalGroupsReport | None,
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inventory: PcbInventoryReport | None = None,
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) -> str:
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"""Plain-text block appended to the schematic neighborhood for PCB review."""
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lines = ["### PCB layout context (existing board — do not move parts)"]
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domain_id = None
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group = None
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if plan is not None:
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for g in plan.groups:
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if g.ref == ic_ref:
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group = g
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break
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for d in plan.domains:
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if ic_ref in d.ic_refs:
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domain_id = d.domain_id
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lines.append(
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f"Domain: {d.domain_id} (power nets: {', '.join(d.power_nets) or '—'})"
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)
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break
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if group is None:
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lines.append("Functional group: (this IC is not in a classified group)")
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else:
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lines.append(
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f"Functional group: {group.ref} subtype={group.component_subtype or '—'} "
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f"rank={group.rank}"
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)
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sats = group.satellites or []
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if sats:
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lines.append("Satellites:")
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for s in sats:
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xy = ""
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if layout and s.ref in layout.footprints:
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fp = layout.footprints[s.ref]
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xy = f" @ ({fp.x:.2f},{fp.y:.2f}) {fp.layer}"
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lines.append(
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f" {s.ref} role={s.role_hint} nets={','.join(s.nets or [])}{xy}"
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)
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else:
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lines.append("Satellites: none")
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if layout and ic_ref in layout.footprints:
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fp = layout.footprints[ic_ref]
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lines.append(
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f"Footprint {ic_ref}: ({fp.x:.2f},{fp.y:.2f}) layer={fp.layer} "
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f"pads={len(fp.pads)}"
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)
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near: list[str] = []
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for other, ofp in layout.footprints.items():
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if other == ic_ref:
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continue
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dist = math.hypot(ofp.x - fp.x, ofp.y - fp.y)
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if dist <= 15.0:
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near.append(f"{other} {dist:.1f}mm {ofp.layer}")
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if near:
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lines.append("Within 15 mm: " + "; ".join(sorted(near)[:24]))
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pin_nets = graph.components.get(ic_ref)
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if pin_nets:
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seen: set[str] = set()
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lines.append("Connected net lengths (PCB copper):")
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for net_name in pin_nets.pins.values():
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if not net_name or net_name in seen:
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continue
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seen.add(net_name)
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mm = net_length_mm(layout, net_name)
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lines.append(f" {net_name}: {mm:.2f} mm")
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lines.append(format_pcb_geometry(ic_ref, graph, layout))
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elif layout is None:
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lines.append("No LayoutGraph — skip millimetre claims.")
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lines.append("### Parsed board geometry (from .kicad_pcb — cite these numbers)")
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lines.append("Vias under footprint: (none)")
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lines.append("Copper thickness: (none in parsed stackup)")
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lines.append("Nearby / pin-net trace widths: (none)")
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lines.append("Board keepout polygons: (none)")
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else:
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lines.append(f"No footprint for {ic_ref} on the PCB.")
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lines.append(format_pcb_geometry(ic_ref, graph, layout))
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if inventory and inventory.nets:
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sample = inventory.nets[:12]
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lines.append("Inventory sample (name length_mm pair):")
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for n in sample:
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lines.append(
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f" {n.name}: {n.length_mm:.2f} mm pair={n.pair or '—'} "
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f"Z0={n.z0_ohm if n.z0_ohm is not None else '—'}"
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)
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if domain_id:
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lines.append(f"(domain_id={domain_id})")
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return "\n".join(lines)
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