michele
c6abdae762
Trace-width vs current runs only with I_load/Imax/I_abs. Missing I is a skip, not INFO INSUFFICIENT, not USB 500 mA, not Iout_max-as-load.
357 lines
12 KiB
Python
357 lines
12 KiB
Python
"""Regression: PCB software false positives (not HubAudio copper)."""
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from __future__ import annotations
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import re
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from pathlib import Path
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from backend.periscopex.bom_pcb_check import check_bom_pcb_datasheet
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from backend.periscopex.emi_check import check_emi
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from backend.periscopex.models import (
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AbsMaxRating,
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Component,
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ComponentConstraints,
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ComponentType,
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DesignGraph,
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InductorSpecs,
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LayoutFootprint,
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LayoutGraph,
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LayoutPad,
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LayoutSegment,
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LayoutZone,
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Net,
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NetType,
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PackageInfo,
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Pin,
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PinConnection,
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ResistorSpecs,
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SimpleComponentSpecs,
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ValueDecoder,
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)
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from backend.periscopex.parsers_kicad_pcb import parse_kicad_pcb
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from backend.periscopex.pcb_checks import unrouted_pad_nets
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from backend.periscopex.pcb_power_thermal import (
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check_pcb_kelvin,
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check_pcb_power_traces,
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check_pcb_via_current,
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)
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from backend.periscopex.pi_check import check_power_integrity
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from backend.periscopex.resolve_passives import decode_value
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from backend.services.passive_from_mpn import specs_from_mpn
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from backend.services.passive_from_value import specs_from_bom_value
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_DRC = Path(__file__).parent / "fixtures" / "HubAudio-DRC.rpt"
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_HUB_PCB = Path(
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"/Users/michelebigi/Development/HubAudio/hardware/kicad/HubAudio/HubAudio.kicad_pcb"
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)
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_KICAD10 = """(kicad_pcb (version 20260206) (generator pcbnew)
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(net "GND")
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(net "+3V3")
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(footprint "R_0603"
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(layer "F.Cu")
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(at 10 10 0)
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(property "Reference" "R1" (at 0 0 0) (effects (font (size 1 1))))
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(pad "1" smd rect (at -0.5 0) (size 0.8 0.9) (layers "F.Cu") (net "+3V3"))
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(pad "2" smd rect (at 0.5 0) (size 0.8 0.9) (layers "F.Cu") (net "GND"))
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)
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(segment (start 10 10) (end 12 10) (width 0.2) (layer "F.Cu") (net "+3V3"))
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(via (at 11 10) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net "GND"))
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)
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"""
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def test_kicad10_name_only_nets_fill_index(tmp_path: Path):
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p = tmp_path / "k10.kicad_pcb"
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p.write_text(_KICAD10)
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g = parse_kicad_pcb(p)
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assert "GND" in g.nets and "+3V3" in g.nets
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assert g.footprints["R1"].pads[0].net == "+3V3"
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assert g.segments[0].net == "+3V3"
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assert g.vias[0].net == "GND"
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def test_lay004_zone_counts_as_copper():
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layout = LayoutGraph(
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footprints={
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"C1": LayoutFootprint(
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reference="C1", x=0, y=0, layer="F.Cu",
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pads=[
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LayoutPad(number="1", x=0, y=0, net="GND"),
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LayoutPad(number="2", x=1, y=0, net="USB_DP"),
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],
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),
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},
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zones=[
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LayoutZone(
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net="GND", layer="In1.Cu",
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outlines=[[(0, 0), (10, 0), (10, 10), (0, 10)]],
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),
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],
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)
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missing = unrouted_pad_nets(layout)
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assert missing == ["USB_DP"]
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def test_lay004_skips_unconnected_nc_and_matches_sheet_prefix():
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layout = LayoutGraph(
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footprints={
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"U1": LayoutFootprint(
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reference="U1", x=0, y=0, layer="F.Cu",
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pads=[
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LayoutPad(number="1", x=0, y=0, net="/Codec/LINE_OUT_R"),
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LayoutPad(number="2", x=1, y=0, net="unconnected-(U1-NC-Pad2)"),
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],
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),
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},
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segments=[
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LayoutSegment(
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start=(0, 0), end=(2, 0), width=0.2, layer="F.Cu",
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net="Codec/LINE_OUT_R",
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),
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],
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)
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assert unrouted_pad_nets(layout) == []
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def test_drc_unconnected_items_count():
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text = _DRC.read_text(encoding="utf-8", errors="replace")
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m = re.search(r"Found (\d+) unconnected pads", text)
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assert m and int(m.group(1)) == 30
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n = len(re.findall(r"^\[unconnected_items\]", text, re.M))
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assert n == 30
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def test_hubaudio_pcb_lay004_vs_drc_order_of_magnitude():
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if not _HUB_PCB.is_file():
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return
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layout = parse_kicad_pcb(_HUB_PCB)
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assert layout.nets, "KiCad 10 name-only nets must fill LayoutGraph.nets"
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missing = unrouted_pad_nets(layout)
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assert len(missing) <= 30, missing[:20]
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assert len(missing) < 139
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def test_ep_split_pads_not_bom_011():
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cons = ComponentConstraints(
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mpn="SW",
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package_info=PackageInfo(base_family="TI", package="SON-8-EP", pin_count=8),
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pintable=[Pin(number=str(i), name=f"P{i}") for i in range(1, 9)],
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absolute_maximum_ratings=[],
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rules=[],
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)
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pads = [LayoutPad(number=str(i), x=0, y=0, net="GND") for i in range(1, 9)]
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pads += [
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LayoutPad(number="9", x=0, y=0, net="GND", pinfunction="EP"),
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LayoutPad(number="9_1", x=0.2, y=0, net="GND"),
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LayoutPad(number="9_2", x=0.4, y=0, net="GND"),
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]
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graph = DesignGraph(
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components={
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"U1": Component(
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reference="U1", value="SW", footprint="SON-8",
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component_type=ComponentType.IC, mpn="SW",
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pins={str(i): "GND" for i in range(1, 9)},
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),
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},
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nets={},
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)
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layout = LayoutGraph(
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footprints={"U1": LayoutFootprint(reference="U1", x=0, y=0, pads=pads)},
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)
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ids = {f.rule_id for f in check_bom_pcb_datasheet(graph, {"SW": cons}, layout)}
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assert "PE-BOM-011" not in ids
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def test_vddcr_absmax_does_not_bind_3v3_io():
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cons = ComponentConstraints(
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mpn="PHY",
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package_info=PackageInfo(base_family="SMS", package="QFN-24", pin_count=24),
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pintable=[
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Pin(number="6", name="VDDCR"),
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Pin(number="8", name="VDDIO"),
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],
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absolute_maximum_ratings=[
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AbsMaxRating(
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parameter="Digital Core Supply Voltage (VDDCR)",
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min=None, max=1.5, unit="V", source_page=52,
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),
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AbsMaxRating(
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parameter="Positive voltage on XTAL2, with respect to ground",
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min=None, max=2.5, unit="V", source_page=52,
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),
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AbsMaxRating(
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parameter="Ground voltage differences VSS to VSS (thermal pad)",
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min=None, max=0.3, unit="V", source_page=7,
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),
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],
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rules=[],
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)
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graph = DesignGraph(
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components={
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"U19": Component(
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reference="U19", value="PHY", footprint="QFN-24",
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component_type=ComponentType.IC, mpn="PHY",
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pins={"6": "Net-VDDCR", "8": "3V3_ETHERNET"},
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),
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},
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nets={
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"3V3_ETHERNET": Net(
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name="3V3_ETHERNET", net_type=NetType.POWER, voltage=3.3,
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pins=[PinConnection(component_ref="U19", pin_number="8")],
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),
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"Net-VDDCR": Net(
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name="Net-VDDCR", net_type=NetType.POWER, voltage=1.2,
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pins=[PinConnection(component_ref="U19", pin_number="6")],
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),
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},
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)
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findings = check_bom_pcb_datasheet(graph, {"PHY": cons}, None)
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assert all(f.rule_id != "PE-BOM-012" for f in findings)
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def test_kelvin_ignores_crs_and_in_plus():
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cons = ComponentConstraints(
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mpn="PHY",
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pintable=[
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Pin(number="11", name="CRS_DV/MODE2", description="carrier sense"),
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Pin(number="10", name="IN+", description="differential input"),
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],
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absolute_maximum_ratings=[],
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rules=[],
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)
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graph = DesignGraph(
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components={
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"U19": Component(
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reference="U19", value="PHY", footprint="",
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component_type=ComponentType.IC, mpn="PHY",
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pins={"11": "ETH_CRS_DV", "10": "VSYS"},
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),
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"R1": Component(
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reference="R1", value="10k", footprint="",
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component_type=ComponentType.RESISTOR, mpn="",
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pins={"1": "ETH_CRS_DV", "2": "VSYS"},
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),
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"U4": Component(
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reference="U4", value="AMP", footprint="",
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component_type=ComponentType.IC, mpn="X",
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pins={"1": "ETH_CRS_DV", "2": "VSYS"},
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),
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},
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nets={},
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)
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assert check_pcb_kelvin(graph, {"PHY": cons}) == []
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def test_emi_and_pi_skip_unconnected_nets():
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cons = ComponentConstraints(
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mpn="MOD",
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pintable=[
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Pin(number="38", name="USB_DN"),
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Pin(number="23", name="NC"),
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Pin(number="31", name="VDD_USB"),
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],
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absolute_maximum_ratings=[],
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rules=[],
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layout_rules=[{
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"kind": "emi",
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"note": "antenna port 50 ohm ferrite",
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"source_page": 12,
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}],
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)
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graph = DesignGraph(
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components={
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"U38": Component(
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reference="U38", value="BT", footprint="",
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component_type=ComponentType.IC, mpn="MOD",
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pins={
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"38": "unconnected-(U38-USB_DN-Pad38)",
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"31": "unconnected-(U38-VDD_USB-Pad31)",
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"23": "unconnected-(U12-NC-Pad23)",
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},
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),
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},
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nets={},
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)
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assert check_emi(graph, {"MOD": cons}, None) == []
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assert check_power_integrity(graph, {"MOD": cons}) == []
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def test_lqw_decoder_and_unknown_skip():
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dec = ValueDecoder(
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type="murata_lqw_inductance", base_unit="nH", output_unit="H",
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)
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assert abs(decode_value("18N", dec) - 18e-9) < 1e-15
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model = specs_from_mpn("LQW18AN18NJ00D")
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assert model is not None
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assert abs(model.specs.value_henries - 18e-9) < 1e-15
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bad = ValueDecoder(type="nope", base_unit="H", output_unit="H")
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try:
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decode_value("18N", bad)
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raise AssertionError("expected unknown decoder")
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except ValueError as exc:
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assert "Unknown decoder type" in str(exc)
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def test_fb1_blm_is_bead_not_dcr_resistor():
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model = specs_from_mpn("BLM18BB600SN1D")
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assert model is not None
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assert model.specs.component_subtype == "passive.ferrite_bead"
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assert model.specs.impedance_ohm == 60.0
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dcr = specs_from_bom_value("BLM18BB600SN1D", "0.25 ohm", "FB")
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assert dcr is not None
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assert dcr.specs.component_subtype == "passive.ferrite_bead"
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assert isinstance(dcr.specs, InductorSpecs)
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assert not isinstance(dcr.specs, ResistorSpecs)
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assert dcr.specs.impedance_ohm == 60.0
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assert getattr(dcr.specs, "value_ohms", None) is None
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def test_via_current_skips_without_i_load():
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from backend.periscopex.models import LayoutStackup
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cons = ComponentConstraints(
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mpn="LDO1",
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pintable=[Pin(number="1", name="VIN"), Pin(number="2", name="VOUT")],
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absolute_maximum_ratings=[],
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rules=[],
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)
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graph = DesignGraph(
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components={
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"U1": Component(
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reference="U1", value="LDO", footprint="",
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component_type=ComponentType.IC, mpn="LDO1",
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pins={"1": "VIN", "2": "VOUT"},
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specs=SimpleComponentSpecs(specs_type="discrete", values={}),
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),
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},
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nets={
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"VOUT": Net(name="VOUT", net_type=NetType.POWER, pins=[]),
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},
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)
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layout = LayoutGraph(
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stackup=LayoutStackup(
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copper_layers=["F.Cu"], dielectrics=[], copper_thickness_mm=0.035,
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),
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footprints={"U1": LayoutFootprint(reference="U1", x=0, y=0, layer="F.Cu")},
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segments=[
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LayoutSegment(start=(0, 0), end=(5, 0), width=0.5, layer="F.Cu", net="VOUT"),
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],
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)
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findings = check_pcb_via_current(graph, {"LDO1": cons}, layout)
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assert findings == []
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pwr = check_pcb_power_traces(graph, {"LDO1": cons}, layout)
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assert pwr == []
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def test_thinking_reasoning_content_echo_still_present():
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from pathlib import Path
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src = (
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Path(__file__).resolve().parents[1]
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/ "periscope" / "src" / "backend" / "services" / "llm" / "deepseek_provider.py"
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)
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text = src.read_text(encoding="utf-8")
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assert "reasoning_content" in text
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assert "asst[\"reasoning_content\"] = reasoning" in text or 'asst["reasoning_content"] = reasoning' in text
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