micheleandCursor 2950446e12 Add Layout F1 functional groups and crystal/NC checks. ...

Write routing-first domain/satellite topology after graph_build, and
flag crystal CL mismatches and NC pins on active nets without inventing
millimetres.

Co-authored-by: Cursor <cursoragent@cursor.com>

2026-09-12 16:22:56 +02:00

..

__init__.py

Pinscope open-source core

2026-07-16 21:29:45 -07:00

bom_match_check.py

Ship Sprint 0 CAD foundations so findings, KiCad hierarchy, BOM match, eval, and optional PCB ingest have a stable contract.

2026-09-10 21:54:37 +02:00

bom_summary.py

Resolve passives from catalog, BOM value, and Murata LQW18AN without an LLM.

2026-08-28 20:25:34 +02:00

cad_bridge.py

Add KiCad cad-bridge JSON and an action plugin for finding focus.

2026-09-10 22:40:28 +02:00

crystal_cl_check.py

Add Layout F1 functional groups and crystal/NC checks.

2026-09-12 16:22:56 +02:00

derating.py

Add DC-bias C_eff stima to derating and INFO when bulk C has no HF ceramic.

2026-09-10 22:23:05 +02:00

dnp_check.py

Add power-margin, PG-to-EN sequencing, and DNP enable checks.

2026-09-10 22:34:06 +02:00

errata_check.py

Add lifecycle, errata, internal-features, and layout_rules checks.

2026-09-10 22:48:27 +02:00

eval_report.py

Add PCB intra-pair skew only when the datasheet gives millimetres.

2026-09-10 23:34:57 +02:00

filter_check.py

Add schematic filter topology and LDO/resistor thermal checks.

2026-09-10 22:28:40 +02:00

functional_groups.py

Add Layout F1 functional groups and crystal/NC checks.

2026-09-12 16:22:56 +02:00

graph.py

Prefer .kicad_pcb pad nets when building the design graph.

2026-09-11 12:39:49 +02:00

hf_coverage_check.py

Add DC-bias C_eff stima to derating and INFO when bulk C has no HF ceramic.

2026-09-10 22:23:05 +02:00

impedance_traces.py

Run ImpedenceFinder Z0 on routed signal nets during project analysis.

2026-09-11 00:21:49 +02:00

impedance.py

Integrate ImpedenceFinder closed-form Z0 into the project Impedance tab.

2026-09-10 23:14:57 +02:00

internal_features_check.py

Add lifecycle, errata, internal-features, and layout_rules checks.

2026-09-10 22:48:27 +02:00

layout_rules.py

Add PCB intra-pair skew only when the datasheet gives millimetres.

2026-09-10 23:34:57 +02:00

led_current_check.py

Pinscope open-source core

2026-07-16 21:29:45 -07:00

library_gate.py

Ship DeepSeek roadmap P0-5/P2 integrations.

2026-09-12 15:48:39 +02:00

lifecycle.py

Add lifecycle, errata, internal-features, and layout_rules checks.

2026-09-10 22:48:27 +02:00

models.py

Run ImpedenceFinder Z0 on routed signal nets during project analysis.

2026-09-11 00:21:49 +02:00

nc_pin_check.py

Add Layout F1 functional groups and crystal/NC checks.

2026-09-12 16:22:56 +02:00

netlist_bundle.py

Accept a KiCad project zip as the upload unit for hierarchical sheets.

2026-09-11 08:15:00 +02:00

parsers_edif.py

Pinscope open-source core

2026-07-16 21:29:45 -07:00

parsers_kicad_pcb.py

Prefer .kicad_pcb pad nets when building the design graph.

2026-09-11 12:39:49 +02:00

parsers_kicad.py

Fix KiCad .kicad_sch power/label net merging.

2026-09-11 12:15:41 +02:00

parsers.py

Add power-margin, PG-to-EN sequencing, and DNP enable checks.

2026-09-10 22:34:06 +02:00

passive_rail_check.py

Size I2C pull-ups, flag NRST pull-downs, and distinguish LDO Cout from MCU decoupling.

2026-09-10 22:07:14 +02:00

pdf_text.py

Ship DeepSeek roadmap P0-5/P2 integrations.

2026-09-12 15:48:39 +02:00

pin_function_tokens.py

Pinscope open-source core

2026-07-16 21:29:45 -07:00

pin_mux_check.py

Ship Sprint 0 CAD foundations so findings, KiCad hierarchy, BOM match, eval, and optional PCB ingest have a stable contract.

2026-09-10 21:54:37 +02:00

placement_check.py

Flag keepout tracks in the courtyard and mark the plan map OK.

2026-09-11 00:11:02 +02:00

power_margin_check.py

Add power-margin, PG-to-EN sequencing, and DNP enable checks.

2026-09-10 22:34:06 +02:00

quote_verify.py

Reconstruct datasheet pages with reading-order blocks and table markdown.

2026-08-28 16:29:52 +02:00

resolve_passives.py

Resolve passives from catalog, BOM value, and Murata LQW18AN without an LLM.

2026-08-28 20:25:34 +02:00

review_fingerprint.py

Default to DeepSeek V4.1 Flash, show API cost in USD, and re-analyze after replacing BOM and netlist.

2026-09-10 20:55:35 +02:00

review_workflow.py

Add finding review states, ECO export, and a report release signature.

2026-09-10 23:21:36 +02:00

sequencing_check.py

Add power-margin, PG-to-EN sequencing, and DNP enable checks.

2026-09-10 22:34:06 +02:00

si_check.py

Add PCB intra-pair skew only when the datasheet gives millimetres.

2026-09-10 23:34:57 +02:00

taxonomy.py

Pinscope open-source core

2026-07-16 21:29:45 -07:00

thermal_check.py

Add power-margin, PG-to-EN sequencing, and DNP enable checks.

2026-09-10 22:34:06 +02:00

utils.py

Pinscope open-source core

2026-07-16 21:29:45 -07:00

validate.py

Verify review quotes against datasheet PDF text and extract ESD Vrwm/polarity.

2026-08-28 15:43:14 +02:00

validation_tools.py

Ship DeepSeek roadmap P0-5/P2 integrations.

2026-09-12 15:48:39 +02:00