michele
342792df2d
ERROR stays only for RULE+MANDATORY. Hierarchy walks component→pin→net→block. Derating is PASS/MARGIN/RISK from Vop/Vrated. Timing and PI skip without numbers. ESD and HS return path are REVIEW, not RULE ERROR.
202 lines
7.9 KiB
Python
202 lines
7.9 KiB
Python
"""Deterministic PCB review checks (no LLM). Fail-soft at the caller."""
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from __future__ import annotations
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import logging
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from collections import Counter
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from backend.periscopex.derating import build_derating_table
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from backend.periscopex.esd_return_check import check_esd, check_return_path
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from backend.periscopex.finding_engine import complete_findings
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from backend.periscopex.functional_groups import FunctionalGroupsReport
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from backend.periscopex.hierarchy import check_hierarchy
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from backend.periscopex.models import DesignGraph, Finding, LayoutGraph
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from backend.periscopex.pcb_net_match import check_pcb_net_match
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from backend.periscopex.pcb_power_thermal import (
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check_pcb_gnd_stitch,
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check_pcb_kelvin,
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check_pcb_power_traces,
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check_pcb_thermal_copper,
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check_pcb_via_current,
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)
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from backend.periscopex.pi_check import check_power_integrity
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from backend.periscopex.placement_check import check_placement
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from backend.periscopex.si_check import check_si
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from backend.periscopex.timing_check import check_timing
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log = logging.getLogger(__name__)
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_FALLBACK_FIX = "Confirm the layout against the datasheet and adjust the board."
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def assign_pcb_finding_ids(findings: list[Finding]) -> None:
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"""IDs ``PCB-{designator}-{001}`` so they never collide with schema review."""
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counter: Counter[str] = Counter()
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for f in findings:
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counter[f.designator] += 1
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f.finding_id = f"PCB-{f.designator}-{counter[f.designator]:03d}"
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rec = (f.recommendation or "").strip()
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act = (f.action or "").strip()
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if not rec:
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rec = act or _FALLBACK_FIX
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f.recommendation = rec
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if not act:
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f.action = rec
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complete_findings(findings)
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def check_pcb_derating(graph: DesignGraph) -> list[Finding]:
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"""PASS / MARGIN / RISK (exceed) when both Vop and Vrated exist."""
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out: list[Finding] = []
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n_pass = 0
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for row in build_derating_table(graph):
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rated = row.get("rated_voltage_v")
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op = row.get("operating_voltage_v")
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stress = row.get("stress") or "UNKNOWN"
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if rated is None or op is None:
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continue
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ref = str(row.get("designator") or "")
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mpn = str(row.get("mpn") or "")
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net = row.get("net_plus")
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ratio = float(op) / float(rated)
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if stress == "RISK":
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rec = (
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f"Replace {ref} with a capacitor rated above {op:g} V, "
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"or lower the rail."
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)
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out.append(Finding(
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designator=ref,
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mpn=mpn,
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aspect="derating",
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finding=(
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f"{ref} operates at {op:g} V with a {rated:g} V rating "
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f"(Vop/Vrated={ratio:.2f})."
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),
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facts=f"Vop={op:g} V, Vrated={rated:g} V, ratio={ratio:.3f}.",
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requirement="Operating voltage must not exceed the capacitor rating.",
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inference="Exceeding Vr is a measured RULE, not a dielectric %.",
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why="Capacitor voltage rating must exceed the rail (no invented derating %).",
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status="ERROR",
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recommendation=rec,
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action=rec,
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source="pcb_derating",
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rule_id="PE-DRT-001",
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evidence_status="SUFFICIENT",
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net=net,
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pins=[],
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))
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elif stress == "MARGIN":
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rec = (
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f"Confirm {ref} voltage margin ({op:g}/{rated:g} V) or pick a "
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"higher Vr. This is utilization, not a 50% ceramic rule."
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)
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out.append(Finding(
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designator=ref,
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mpn=mpn,
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aspect="derating",
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finding=(
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f"{ref} Vop/Vrated={ratio:.2f} ({op:g}/{rated:g} V) — MARGIN."
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),
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facts=f"Vop={op:g} V, Vrated={rated:g} V, ratio={ratio:.3f}.",
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requirement="Utilization > 0.8 of Vr is flagged as MARGIN (RISK).",
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inference="Not an invented IPC/ceramic derating percentage.",
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why="PASS/MARGIN/RISK from Vop and Vrated only.",
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status="WARNING",
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recommendation=rec,
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action=rec,
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source="pcb_derating",
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rule_id="PE-DRT-002",
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evidence_status="SUFFICIENT",
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net=net,
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pins=[],
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))
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elif stress == "PASS":
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n_pass += 1
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if n_pass:
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rec = "No voltage-rating change required for PASS capacitors."
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out.append(Finding(
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designator="C",
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mpn="",
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aspect="derating",
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finding=f"{n_pass} capacitor(s) PASS (Vop/Vrated ≤ 0.8).",
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facts=f"PASS count={n_pass} (both Vop and Vrated present).",
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requirement="Rated voltage exists and Vop is ≤ 80% of Vr.",
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inference="Summary INFO — per-cap PASS lives on the derating table.",
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why="Avoid one INFO card per capacitor.",
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status="INFO",
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recommendation=rec,
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action=rec,
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source="pcb_derating",
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rule_id="PE-DRT-003",
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evidence_status="SUFFICIENT",
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pins=[],
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))
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return out
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def merge_schema_pcb_reports(
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schema: dict | None, pcb: dict | None,
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) -> dict | None:
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"""Combine schematic report.json with pcb_report.json for GET /report."""
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if not schema and not pcb:
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return None
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if not pcb:
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out = dict(schema or {})
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out["findings"] = [
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f for f in (out.get("findings") or [])
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if not str(f.get("finding_id") or "").startswith("PCB-")
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]
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return out
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if not schema:
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return dict(pcb)
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findings = [
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f for f in (schema.get("findings") or [])
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if not str(f.get("finding_id") or "").startswith("PCB-")
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]
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findings.extend(pcb.get("findings") or [])
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out = dict(schema)
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out["findings"] = findings
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summary: dict[str, int] = {"ERROR": 0, "WARNING": 0, "INFO": 0}
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for f in findings:
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st = f.get("status")
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if st in summary:
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summary[st] = summary.get(st, 0) + 1
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out["summary"] = summary
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schema_nr = list((schema or {}).get("not_reviewed") or [])
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pcb_nr = list((pcb or {}).get("not_reviewed") or [])
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if schema_nr or pcb_nr:
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out["not_reviewed"] = schema_nr + pcb_nr
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return out
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def run_pcb_checks(
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graph: DesignGraph,
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constraints_map: dict,
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layout: LayoutGraph | None,
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plan: FunctionalGroupsReport | None = None,
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) -> list[Finding]:
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"""Placement, SI, pad-net match, derating, hierarchy, timing, PI, ESD."""
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out: list[Finding] = []
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for name, fn in (
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("pcb_net_match", lambda: check_pcb_net_match(graph, layout)),
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("placement_check", lambda: check_placement(graph, constraints_map, layout)),
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("si_check", lambda: check_si(graph, constraints_map, layout)),
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("pcb_derating", lambda: check_pcb_derating(graph)),
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("pcb_power_traces", lambda: check_pcb_power_traces(graph, constraints_map, layout)),
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("pcb_via_current", lambda: check_pcb_via_current(graph, constraints_map, layout)),
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("pcb_thermal_copper", lambda: check_pcb_thermal_copper(graph, constraints_map, layout)),
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("pcb_kelvin", lambda: check_pcb_kelvin(graph, constraints_map)),
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("pcb_gnd_stitch", lambda: check_pcb_gnd_stitch(graph, layout)),
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("hierarchy_check", lambda: check_hierarchy(graph, plan)),
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("timing_check", lambda: check_timing(graph, constraints_map)),
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("pi_check", lambda: check_power_integrity(graph, constraints_map, layout)),
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("esd_check", lambda: check_esd(graph, constraints_map)),
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("return_path", lambda: check_return_path(graph, layout)),
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):
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try:
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out.extend(fn())
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except Exception:
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log.exception("PCB check %s failed — skipping", name)
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assign_pcb_finding_ids(out)
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return out
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