micheleandCursor
78013bd404
Compare only specified IQ plus I_load to Iout_max and series-R drop, flag sequencing only when power_sequence is in specs, and treat DNP as a fitted-variant graph so a missing enable pull is ERROR only when the BOM actually marks DNP. Co-authored-by: Cursor <cursoragent@cursor.com>
110 lines
3.6 KiB
Python
110 lines
3.6 KiB
Python
"""Power-good → enable sequencing when the IC specs declare a sequence.
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No RC time constants are invented. Missing power_sequence means skip.
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"""
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from __future__ import annotations
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import re
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from backend.pinscopex.models import (
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ComponentConstraints,
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ComponentType,
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DesignGraph,
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Finding,
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)
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from backend.pinscopex.thermal_check import (
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_VIN_PIN,
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_VOUT_PIN,
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_is_ldo,
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_pin_net_by_role,
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_specs_values,
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)
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from backend.pinscopex.validate import _match_constraints
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_PG_RE = re.compile(r"(?:^|[_/])(PG|PGOOD|PWRGD|POWER_GOOD|POK)(?:$|[_/\d])", re.I)
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_EN_RE = re.compile(
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r"(?:^|[_/])(EN|ENA|ENABLE|n?SHDN|nEN|EN_N)(?:$|[_/\d])",
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re.I,
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)
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def _has_sequence(comp) -> bool:
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values = _specs_values(comp)
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raw = values.get("power_sequence")
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if raw is None or raw == "" or raw is False:
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return False
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if isinstance(raw, (int, float)) and raw == 0:
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return False
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return True
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def check_power_sequencing(
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graph: DesignGraph,
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constraints_map: dict[str, ComponentConstraints] | None = None,
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) -> list[Finding]:
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cmap = constraints_map or {}
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regs: list[tuple] = []
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for ref, comp in sorted(graph.components.items()):
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if comp.component_type != ComponentType.IC:
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continue
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cons = _match_constraints(comp.mpn or comp.value, cmap)
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vin = _pin_net_by_role(graph, comp, cons, _VIN_PIN)
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vout = _pin_net_by_role(graph, comp, cons, _VOUT_PIN)
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if not (vin and vout) and not _is_ldo(comp, cons):
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continue
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pg = _pin_net_by_role(graph, comp, cons, _PG_RE, exclude_re=None)
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en = _pin_net_by_role(graph, comp, cons, _EN_RE, exclude_re=None)
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regs.append((ref, comp, cons, vin, vout, pg, en))
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findings: list[Finding] = []
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for dref, dcomp, dcons, dvin, _dvout, _dpg, den in regs:
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if not _has_sequence(dcomp):
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continue
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if not den or not dvin:
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continue
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upstream = [
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row for row in regs
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if row[0] != dref and row[4] and row[4] == dvin
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]
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if not upstream:
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continue
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uref, ucomp, _ucons, _uvin, _uvout, upg, _uen = upstream[0]
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if not upg:
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findings.append(Finding(
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designator=dref,
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mpn=dcomp.mpn or "",
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aspect="sequencing",
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source="sequencing_check",
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status="WARNING",
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finding=(
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f"{dref} specs declare power_sequence but upstream {uref} "
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f"has no PG pin feeding {dref} EN '{den}'."
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),
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why="Sequence was listed in IC specs; delay milliseconds were not estimated.",
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recommendation="Tie the upstream power-good to this enable, or remove the sequence spec if unused.",
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reference="power_sequence",
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net=den,
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pins=[dref, uref],
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rule_id="PS-SEQ-001",
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))
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continue
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if upg != den:
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findings.append(Finding(
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designator=dref,
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mpn=dcomp.mpn or "",
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aspect="sequencing",
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source="sequencing_check",
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status="WARNING",
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finding=(
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f"{uref} PG '{upg}' does not connect to {dref} EN '{den}'."
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),
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why="Declared power_sequence expects PG to enable the next rail.",
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recommendation="Net the upstream PG to the downstream EN.",
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reference="power_sequence",
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net=den,
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pins=[f"{uref}", f"{dref}"],
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rule_id="PS-SEQ-001",
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))
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return findings
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