michele
c362ef8a56
Keep validate.py and the finding engine as-is. AGPL LICENSE stays at the repo root. Docker overlays dependency then src. Do not delete the inherited tree.
270 lines
11 KiB
Python
270 lines
11 KiB
Python
"""Pin-mux feasibility check — net-asserted peripheral function vs. the pin's
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silicon alternate-function table.
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Locks in:
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1. A net asserting a function the pin can't be muxed to (UART5_TX on an RX-only
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pin) is a hard ERROR.
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2. A correct assignment produces nothing.
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3. DIRECTION is never flagged: an inter-device same-peripheral link (crossover /
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transceiver) is skipped, not flagged.
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4. Empty functions / opaque nets are skipped.
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5. Deterministic findings carry source="pin_mux_check" and never source_page.
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"""
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from __future__ import annotations
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from tests.paths import SIMPLE_PROJECT, TAXONOMY
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from backend.periscopex.models import (
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Component,
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ComponentConstraints,
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ComponentType,
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DesignGraph,
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Finding,
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Net,
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NetType,
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Pin,
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PinConnection,
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ValidationReport,
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)
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from backend.periscopex.pin_function_tokens import normalize_functions, parse_net_token
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from backend.periscopex.pin_mux_check import check_pin_mux_feasibility
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def _constraints(mpn, pintable):
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return ComponentConstraints(mpn=mpn, pintable=pintable,
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absolute_maximum_ratings=[], rules=[])
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def _ic(ref, mpn, pins):
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return Component(reference=ref, value="", footprint="",
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component_type=ComponentType.IC, mpn=mpn, pins=pins)
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def _graph(components, nets):
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"""nets: {net_name: [(ref, pin_num), ...]}"""
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net_objs = {
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name: Net(name=name, net_type=NetType.SIGNAL,
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pins=[PinConnection(component_ref=r, pin_number=str(p)) for r, p in conns])
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for name, conns in nets.items()
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}
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return DesignGraph(components=components, nets=net_objs)
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# STM32-style: PD2 (pin 54) does UART5_RX only; PC12 (pin 53) does UART5_TX only.
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_PD2 = Pin(number=54, name="PD2", functions=["TIM3_ETR", "UART5_RX", "EVENTOUT"])
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_PC12 = Pin(number=53, name="PC12", functions=["SPI3_MOSI/I2S3_SDO", "UART5_TX"])
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def test_real_defect_uart5_swapped_is_error():
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# Net labels assert TX on the RX-only pin and RX on the TX-only pin.
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u3 = _ic("U3", "MCUX", {"54": "MCU-UART5-TX", "53": "MCU-UART5-RX"})
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g = _graph({"U3": u3},
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{"MCU-UART5-TX": [("U3", 54)], "MCU-UART5-RX": [("U3", 53)]})
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cmap = {"MCUX": _constraints("MCUX", [_PD2, _PC12])}
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findings = check_pin_mux_feasibility(g, cmap)
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assert len(findings) == 2
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assert all(f.status == "ERROR" for f in findings)
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assert all(f.source == "pin_mux_check" for f in findings)
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assert all(f.source_page is None for f in findings)
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assert {f.designator for f in findings} == {"U3"}
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tx = next(f for f in findings if "MCU-UART5-TX" in f.finding)
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assert "cannot be muxed as UART5_TX" in tx.finding
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assert tx.rule_id == "PE-MUX-001"
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assert tx.net == "MCU-UART5-TX"
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assert tx.pins == ["U3.54"]
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def test_correct_assignment_no_finding():
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u3 = _ic("U3", "MCUX", {"54": "MCU-UART5-RX", "53": "MCU-UART5-TX"})
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g = _graph({"U3": u3},
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{"MCU-UART5-RX": [("U3", 54)], "MCU-UART5-TX": [("U3", 53)]})
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cmap = {"MCUX": _constraints("MCUX", [_PD2, _PC12])}
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assert check_pin_mux_feasibility(g, cmap) == []
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def test_inter_device_same_peripheral_link_is_skipped():
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# A correct crossover: the net named from U3's TX perspective also lands on a
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# peer IC pin that exposes UART5. Direction is the reviewer's call -> skip.
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u3 = _ic("U3", "MCUX", {"54": "MCU-UART5-TX"})
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peer = _ic("U7", "PEER", {"5": "MCU-UART5-TX"})
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g = _graph({"U3": u3, "U7": peer},
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{"MCU-UART5-TX": [("U3", 54), ("U7", 5)]})
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cmap = {
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"MCUX": _constraints("MCUX", [_PD2]),
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"PEER": _constraints("PEER", [Pin(number=5, name="RXD", functions=["UART5_TX"])]),
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}
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assert check_pin_mux_feasibility(g, cmap) == []
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def test_transceiver_peer_without_peripheral_still_fires():
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# Peer pin is a transceiver "DI" with no UART peripheral -> gate does NOT
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# apply; the MCU pin is still genuinely infeasible -> ERROR.
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u3 = _ic("U3", "MCUX", {"54": "MCU-UART5-TX"})
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xcvr = _ic("U9", "XCVR", {"1": "MCU-UART5-TX"})
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g = _graph({"U3": u3, "U9": xcvr},
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{"MCU-UART5-TX": [("U3", 54), ("U9", 1)]})
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cmap = {
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"MCUX": _constraints("MCUX", [_PD2]),
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"XCVR": _constraints("XCVR", [Pin(number=1, name="DI", functions=["DI"])]),
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}
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findings = check_pin_mux_feasibility(g, cmap)
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assert len(findings) == 1 and findings[0].status == "ERROR"
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def test_empty_functions_skipped():
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u3 = _ic("U3", "MCUX", {"54": "MCU-UART5-TX"})
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g = _graph({"U3": u3}, {"MCU-UART5-TX": [("U3", 54)]})
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cmap = {"MCUX": _constraints("MCUX", [Pin(number=54, name="PD2", functions=None)])}
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assert check_pin_mux_feasibility(g, cmap) == []
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def test_pin_exposes_peripheral_but_not_signal_no_complement():
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# Net asserts I2C1_SDA on a pin that exposes I2C1 only as SCL -> infeasible.
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u3 = _ic("U3", "MCUX", {"20": "I2C1-SDA-3V3"})
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g = _graph({"U3": u3}, {"I2C1-SDA-3V3": [("U3", 20)]})
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cmap = {"MCUX": _constraints("MCUX", [Pin(number=20, name="PB8", functions=["I2C1_SCL"])])}
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findings = check_pin_mux_feasibility(g, cmap)
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assert len(findings) == 1 and findings[0].status == "ERROR"
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def test_opaque_net_not_flagged():
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u3 = _ic("U3", "MCUX", {"54": "NetC7_1"})
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g = _graph({"U3": u3}, {"NetC7_1": [("U3", 54)]})
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cmap = {"MCUX": _constraints("MCUX", [_PD2])}
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assert check_pin_mux_feasibility(g, cmap) == []
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def test_token_parser_and_normalizer():
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assert parse_net_token("MCU-UART5-TX") == ("UART5", "TX")
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assert parse_net_token("I2C1-SDA-3V3") == ("I2C1", "SDA")
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assert parse_net_token("/UART0.TX") == ("UART0", "TX")
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assert parse_net_token("SPI2-CS") == ("SPI2", "NSS") # CS canonicalises to NSS
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assert parse_net_token("NetC7_1") is None
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assert parse_net_token("+5V") is None
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assert ("UART5", "RX") in normalize_functions(["TIM3_ETR", "UART5_RX"])
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assert normalize_functions(["SPI3_MOSI/I2S3_SDO"]) >= {("SPI3", "MOSI")}
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# TI MSPM0-style pintable: modern controller/peripheral SPI nomenclature.
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# PB17 (pin 36) exposes SPI0 as PICO (== MOSI); PB19 (pin 38) as POCI (== MISO).
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_PB17 = Pin(number=36, name="PB17", functions=["UART2_TX", "SPI0_PICO", "SPI1_CS1"])
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_PB19 = Pin(number=38, name="PB19", functions=["SPI0_POCI", "UART0_CTS"])
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def test_spi_legacy_net_names_match_modern_pin_functions():
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# Regression for the U3-001/U3-002 false positives: net labels use legacy
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# MOSI/MISO, the datasheet uses PICO/POCI — the same physical lines. No
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# finding: PICO≡MOSI, POCI≡MISO.
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u3 = _ic("U3", "MSPM0G3507SPTR", {"36": "/SPI0.MOSI", "38": "/SPI0.MISO"})
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g = _graph({"U3": u3},
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{"/SPI0.MOSI": [("U3", 36)], "/SPI0.MISO": [("U3", 38)]})
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cmap = {"MSPM0G3507SPTR": _constraints("MSPM0G3507SPTR", [_PB17, _PB19])}
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assert check_pin_mux_feasibility(g, cmap) == []
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def test_spi_controller_peripheral_names_are_synonyms():
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assert parse_net_token("/SPI0.MOSI") == ("SPI0", "MOSI")
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assert parse_net_token("/SPI0.PICO") == ("SPI0", "MOSI")
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assert parse_net_token("SPI0-COPI") == ("SPI0", "MOSI")
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assert parse_net_token("/SPI0.MISO") == ("SPI0", "MISO")
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assert parse_net_token("/SPI0.POCI") == ("SPI0", "MISO")
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assert parse_net_token("SPI0-CIPO") == ("SPI0", "MISO")
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# Datasheet function strings collapse to the same canonical tokens.
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assert normalize_functions(["SPI0_PICO"]) == {("SPI0", "MOSI")}
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assert normalize_functions(["SPI0_POCI"]) == {("SPI0", "MISO")}
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# Indexed chip-select variants canonicalise to NSS.
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assert normalize_functions(["SPI0_CS0", "SPI1_CS3"]) == {
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("SPI0", "NSS"), ("SPI1", "NSS")}
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assert normalize_functions(["SPI0_STE0"]) == {("SPI0", "NSS")}
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def test_simple_project_uart0_nets_are_feasible_on_mspm0_pins():
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from pathlib import Path
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from backend.periscopex.models import DesignGraph
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graph = DesignGraph.model_validate_json(
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(SIMPLE_PROJECT / "design_graph.json").read_text()
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)
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cmap = {
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"MSPM0G3507SPTR": _constraints(
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"MSPM0G3507SPTR",
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[
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Pin(number=1, name="PA11", functions=["UART0_TX", "SPI1_CS1"]),
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Pin(number=2, name="PA12", functions=["UART0_RX", "SPI1_CS0"]),
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],
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)
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}
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findings = check_pin_mux_feasibility(graph, cmap)
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uart = [f for f in findings if f.net and "UART0" in f.net]
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assert uart == []
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def test_simple_project_uart0_swapped_on_mspm0_is_error():
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from pathlib import Path
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from backend.periscopex.models import DesignGraph
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graph = DesignGraph.model_validate_json(
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(SIMPLE_PROJECT / "design_graph.json").read_text()
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)
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cmap = {
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"MSPM0G3507SPTR": _constraints(
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"MSPM0G3507SPTR",
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[
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Pin(number=1, name="PA11", functions=["UART0_RX"]),
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Pin(number=2, name="PA12", functions=["UART0_TX"]),
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],
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)
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}
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findings = check_pin_mux_feasibility(graph, cmap)
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nets = {f.net for f in findings}
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assert "/UART0.TX" in nets
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assert "/UART0.RX" in nets
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assert all(f.status == "ERROR" for f in findings if f.net and "UART0" in f.net)
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def test_spi_genuine_infeasibility_still_fires_with_modern_names():
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# Net asserts SPI0_MOSI on a pin that exposes SPI0 only as POCI (==MISO) —
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# genuinely infeasible even after synonym collapse -> ERROR.
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u3 = _ic("U3", "MSPM0G3507SPTR", {"38": "/SPI0.MOSI"})
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g = _graph({"U3": u3}, {"/SPI0.MOSI": [("U3", 38)]})
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cmap = {"MSPM0G3507SPTR": _constraints("MSPM0G3507SPTR", [_PB19])}
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findings = check_pin_mux_feasibility(g, cmap)
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assert len(findings) == 1 and findings[0].status == "ERROR"
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# POCI==MISO is the complement of MOSI -> phrased as a likely swap.
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assert "swapped" in findings[0].why
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def test_finding_prints_full_raw_capability_list_and_intent_caveat():
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# Net asserts I2C1_SDA on a pin that exposes I2C1 only as SCL -> infeasible.
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# The finding's `why` must (a) print the pin's full raw alternate-function
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# list verbatim, and (b) state the intent was inferred from the net name.
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pin = Pin(number=20, name="PB8", functions=["I2C1_SCL", "TIMA0_C1", "UART1_RX"])
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u3 = _ic("U3", "MCUX", {"20": "I2C1-SDA-3V3"})
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g = _graph({"U3": u3}, {"I2C1-SDA-3V3": [("U3", 20)]})
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cmap = {"MCUX": _constraints("MCUX", [pin])}
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f = check_pin_mux_feasibility(g, cmap)[0]
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# (a) every raw datasheet function string appears verbatim in `why`.
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for fn in ("I2C1_SCL", "TIMA0_C1", "UART1_RX"):
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assert fn in f.why
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# (b) the inferred-from-net-name caveat is present.
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assert "inferred from the net name" in f.why
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def test_legacy_report_without_source_validates():
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# Backward-compat: a report.json from before these fields existed.
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legacy = {
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"finding_id": "U1-001", "designator": "U1", "mpn": "X",
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"finding": "f", "why": "w", "source_page": 3, "status": "WARNING",
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}
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f = Finding.model_validate(legacy)
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assert f.source is None
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rep = ValidationReport.model_validate({
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"project": "p", "timestamp": "t", "findings": [legacy],
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"summary": {"total": 1}, "coverage": {}, "review_errors": {},
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})
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assert rep.not_reviewed == []
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