michele
4df04df5d4
Add /api/library datasheet import and component GET/PUT with no exam. Reorganize pytest into datasheet, library, schematic, PCB, and AF+AI. Document Rust criteria (none chosen; no rustup) and coding conformity.
100 lines
3.3 KiB
Python
100 lines
3.3 KiB
Python
"""Crystal CL check — only fires when CL and cap values are known."""
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from __future__ import annotations
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from tests.paths import SIMPLE_PROJECT, TAXONOMY
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from backend.periscopex.crystal_cl_check import check_crystal_cl
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from backend.periscopex.models import (
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Component,
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ComponentType,
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DesignGraph,
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Net,
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NetType,
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PinConnection,
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SimpleComponentSpecs,
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)
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def _xtal_graph(*, cl_f: float | None, c1: str, c2: str, stray: float | None = None) -> DesignGraph:
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values: dict = {}
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if cl_f is not None:
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values["load_capacitance_f"] = cl_f
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if stray is not None:
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values["stray_capacitance_f"] = stray
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return DesignGraph(
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components={
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"X1": Component(
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reference="X1",
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value="8MHz",
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footprint="",
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component_type=ComponentType.CRYSTAL,
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mpn="XTAL",
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pins={"1": "XIN", "2": "XOUT", "3": "GND"},
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specs=SimpleComponentSpecs(specs_type="crystal", values=values) if values else None,
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),
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"C1": Component(
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reference="C1", value=c1, footprint="",
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component_type=ComponentType.CAPACITOR,
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pins={"1": "XIN", "2": "GND"},
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),
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"C2": Component(
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reference="C2", value=c2, footprint="",
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component_type=ComponentType.CAPACITOR,
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pins={"1": "XOUT", "2": "GND"},
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),
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},
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nets={
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"XIN": Net(
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name="XIN", net_type=NetType.SIGNAL,
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pins=[
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PinConnection(component_ref="X1", pin_number="1"),
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PinConnection(component_ref="C1", pin_number="1"),
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],
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),
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"XOUT": Net(
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name="XOUT", net_type=NetType.SIGNAL,
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pins=[
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PinConnection(component_ref="X1", pin_number="2"),
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PinConnection(component_ref="C2", pin_number="1"),
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],
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),
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"GND": Net(
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name="GND", net_type=NetType.GROUND,
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pins=[
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PinConnection(component_ref="X1", pin_number="3"),
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PinConnection(component_ref="C1", pin_number="2"),
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PinConnection(component_ref="C2", pin_number="2"),
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],
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),
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},
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)
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def test_no_cl_in_specs_is_silent():
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g = _xtal_graph(cl_f=None, c1="18p", c2="18p")
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assert check_crystal_cl(g) == []
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def test_series_above_cl_without_stray_warns():
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# series of 22p || 22p = 11p — wait we need series > CL.
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# 100p || 100p = 50p > CL 18p * 1.25
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g = _xtal_graph(cl_f=18e-12, c1="100p", c2="100p")
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findings = check_crystal_cl(g)
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assert any(f.rule_id == "PE-XTAL-002" for f in findings)
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def test_with_stray_mismatch_warns():
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# 18p||18p = 9p + 2p stray = 11p vs CL 18p → below 0.75*18
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g = _xtal_graph(cl_f=18e-12, c1="18p", c2="18p", stray=2e-12)
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findings = check_crystal_cl(g)
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assert any(f.rule_id == "PE-XTAL-002" for f in findings)
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def test_simple_project_without_cl_silent():
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from pathlib import Path
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from backend.periscopex.models import DesignGraph
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path = SIMPLE_PROJECT / "design_graph.json"
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g = DesignGraph.model_validate_json(path.read_text())
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assert check_crystal_cl(g) == []
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