micheleandCursor
8d2b85600f
Rename the core package to periscopex, update UI/docs/Docker/deploy defaults to periscope.michelebigi.it, and keep legacy version/storage key aliases so existing projects keep working. Co-authored-by: Cursor <cursoragent@cursor.com>
110 lines
3.1 KiB
Python
110 lines
3.1 KiB
Python
"""DC-bias C_eff stima — not a Murata lot curve.
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Favor: C0G stays at C; X7R at 50% Vr loses ~30%; C_eff formatted.
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Against: tantalum uses C_nom (no MLCC model); missing Vr or C skips C_eff;
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C0G is not treated as X7R.
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"""
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from __future__ import annotations
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from backend.periscopex.derating import (
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build_derating_table,
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dc_bias_remaining,
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)
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from backend.periscopex.models import (
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CapacitorSpecs,
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Component,
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ComponentType,
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DesignGraph,
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Net,
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NetType,
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PinConnection,
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)
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def test_c0g_keeps_full_capacitance():
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assert dc_bias_remaining("C0G", v_op=16.0, rated_v=16.0) == 1.0
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assert dc_bias_remaining("NP0", v_op=10.0, rated_v=16.0) == 1.0
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def test_x7r_at_half_rated_is_about_70_percent():
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f = dc_bias_remaining("X7R", v_op=8.0, rated_v=16.0)
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assert f is not None
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assert 0.65 <= f <= 0.75
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def test_x7r_at_zero_bias_is_nominal():
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assert dc_bias_remaining("X7R", v_op=0.0, rated_v=16.0) == 1.0
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def test_tantalum_has_no_mlcc_bias_model():
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assert dc_bias_remaining("tantalum", v_op=8.0, rated_v=16.0) is None
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def test_missing_voltage_or_value_skips_c_eff():
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assert dc_bias_remaining("X7R", v_op=None, rated_v=16.0) is None
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assert dc_bias_remaining("X7R", v_op=8.0, rated_v=None) is None
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def _cap(ref, dielectric, farads, rated, net="3V3"):
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return Component(
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reference=ref, value="", footprint="",
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component_type=ComponentType.CAPACITOR,
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component_subtype="passive.capacitor.ceramic",
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mpn=ref,
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pins={"1": net, "2": "GND"},
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specs=CapacitorSpecs(
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value_farads=farads,
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value_formatted="10uF",
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voltage_rating_v=f"{rated}V",
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dielectric=dielectric,
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),
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)
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def test_derating_row_includes_c_eff_stima():
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c1 = _cap("C1", "X7R", 10e-6, 16)
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g = DesignGraph(
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components={
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"C1": c1,
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},
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nets={
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"3V3": Net(
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name="3V3", net_type=NetType.POWER, voltage=8.0,
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pins=[PinConnection(component_ref="C1", pin_number="1")],
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),
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"GND": Net(
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name="GND", net_type=NetType.GROUND, voltage=0.0,
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pins=[PinConnection(component_ref="C1", pin_number="2")],
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),
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},
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)
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rows = build_derating_table(g)
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assert len(rows) == 1
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row = rows[0]
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assert row["dc_bias_model"] == "stima"
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assert row["c_nominal_f"] == 10e-6
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assert row["c_eff_f"] is not None
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assert 6.5e-6 <= row["c_eff_f"] <= 7.5e-6
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assert "uF" in (row["c_eff_formatted"] or "")
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def test_c0g_row_c_eff_equals_nominal():
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c1 = _cap("C9", "C0G", 18e-12, 50)
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g = DesignGraph(
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components={"C9": c1},
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nets={
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"3V3": Net(
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name="3V3", net_type=NetType.POWER, voltage=3.3,
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pins=[PinConnection(component_ref="C9", pin_number="1")],
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),
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"GND": Net(
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name="GND", net_type=NetType.GROUND,
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pins=[PinConnection(component_ref="C9", pin_number="2")],
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),
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},
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)
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row = build_derating_table(g)[0]
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assert row["c_eff_f"] == 18e-12
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assert row["dc_bias_factor"] == 1.0
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