michele
4df04df5d4
Add /api/library datasheet import and component GET/PUT with no exam. Reorganize pytest into datasheet, library, schematic, PCB, and AF+AI. Document Rust criteria (none chosen; no rustup) and coding conformity.
114 lines
3.3 KiB
Python
114 lines
3.3 KiB
Python
"""PADS-PCB netlist parser — section-marker robustness.
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Regression coverage for EasyEDA Pro exports, which decorate section headers
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with trailing labels (``*PART* ITEMS``) and append a ``*MISC*
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ATTRIBUTE VALUES`` block after the connectivity. Earlier versions did
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exact-string matching on section markers, so:
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1. The decorated ``*PART*`` header was not recognised — no real parts
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were collected.
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2. The unrecognised ``*MISC*`` block leaked into the net section, where
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``"Datasheet" https://...`` and ``"Footprint" C0603_L1.6-W0.8-H0.8``
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tokens were misparsed as ``ref.pin`` pin connections, polluting the
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graph with phantom components.
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"""
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from __future__ import annotations
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from backend.periscopex.parsers import parse_netlist
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EASYEDA_PRO_NETLIST = """\
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!PADS-POWERPCB-V9.0-MILS-CP936! Created by EasyEDA Pro V2.2.47.7
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*REMARK* Smart Gas Cap_1 -- 2026-04-25 14:52:03
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*REMARK*
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*PART* ITEMS
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U1 RP2040@LQFN-56_L7.0-W7.0-P0.4-EP
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C1 CAI0603X7R105K250JT@C0603
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R1 FRC0603J105 TS@R0603
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*NET*
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*SIGNAL* GND
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U1.19 C1.1 R1.1
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*SIGNAL* +3V3
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U1.1 C1.2 R1.2
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*MISC* MISCELLANEOUS PARAMETERS
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ATTRIBUTE VALUES
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{
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PART U1
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{
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"Manufacturer Part" RP2040
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"Datasheet" https://item.szlcsc.com/datasheet/RP2040/2392.html
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"Footprint" LQFN-56_L7.0-W7.0-P0.4-EP
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"3D Model Title" LQFN-56_L7.0-W7.0-P0.4-EP
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"Description" Voltage Range:2.7V~3.6V Current:100mA
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}
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PART C1
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{
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"Datasheet" https://item.szlcsc.com/datasheet/CAI0603X7R105K250JT/51675802.html
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"3D Model Title" C0603_L1.6-W0.8-H0.8
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}
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}
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*END* OF ASCII OUTPUT FILE
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"""
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def test_easyeda_pro_misc_section_does_not_pollute_nets(tmp_path):
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"""*MISC* attribute block must not leak into net connectivity."""
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netlist_path = tmp_path / "netlist.asc"
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netlist_path.write_text(EASYEDA_PRO_NETLIST)
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known_refs = {"U1", "C1", "R1"}
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parts, nets = parse_netlist(netlist_path, known_refs=known_refs)
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assert set(parts.keys()) == {"U1", "C1", "R1"}, (
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f"phantom parts leaked from *MISC* block: "
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f"{set(parts.keys()) - {'U1', 'C1', 'R1'}}"
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)
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assert set(nets.keys()) == {"GND", "+3V3"}
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all_refs = {ref for pin_list in nets.values() for ref, _ in pin_list}
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assert all_refs <= known_refs, (
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f"phantom refs in nets from *MISC* misparse: {all_refs - known_refs}"
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)
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def test_decorated_part_header_is_recognised(tmp_path):
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"""``*PART* ITEMS`` (with trailing label) must enter the part section."""
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netlist_path = tmp_path / "netlist.asc"
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netlist_path.write_text(
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"*PART* ITEMS\n"
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"U1 RP2040@LQFN-56\n"
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"C1 CAP@C0603\n"
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"*NET*\n"
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"*SIGNAL* GND\n"
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"U1.19 C1.1\n"
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"*END*\n"
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)
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parts, nets = parse_netlist(netlist_path)
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assert parts == {"U1": "RP2040@LQFN-56", "C1": "CAP@C0603"}
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assert nets == {"GND": [("U1", "19"), ("C1", "1")]}
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def test_part_section_without_trailing_label_still_parses(tmp_path):
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"""Plain ``*PART*`` header (no trailing label) must still be recognised."""
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netlist_path = tmp_path / "netlist.asc"
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netlist_path.write_text(
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"*PADS-PCB*\n"
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"*PART*\n"
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"U1 RP2040@LQFN-56\n"
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"*NET*\n"
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"*SIGNAL* GND\n"
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"U1.1\n"
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"*END*\n"
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)
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parts, nets = parse_netlist(netlist_path)
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assert parts == {"U1": "RP2040@LQFN-56"}
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assert nets == {"GND": [("U1", "1")]}
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