michele
4df04df5d4
Add /api/library datasheet import and component GET/PUT with no exam. Reorganize pytest into datasheet, library, schematic, PCB, and AF+AI. Document Rust criteria (none chosen; no rustup) and coding conformity.
127 lines
4.4 KiB
Python
127 lines
4.4 KiB
Python
"""Partial PCB: footprints with few tracks still parse and run MODE=pcb checks."""
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from __future__ import annotations
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from pathlib import Path
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from backend.periscopex.models import (
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Component,
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ComponentType,
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DesignGraph,
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Net,
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NetType,
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)
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from backend.periscopex.parsers_kicad_pcb import parse_kicad_pcb
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from backend.periscopex.pcb_checks import run_pcb_checks
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from backend.periscopex.pcb_net_match import check_pcb_net_match
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from backend.periscopex.placement_check import check_placement
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_PARTIAL = """(kicad_pcb (version 20240108) (generator pcbnew)
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(net 0 "")
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(net 1 "GND")
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(net 2 "+3V3")
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(net 3 "USB_DP")
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(footprint "Package_SO:SOIC-8"
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(layer "F.Cu")
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(at 20 10 0)
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(property "Reference" "U1" (at 0 0 0) (effects (font (size 1 1))))
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(pad "1" smd rect (at -2 1) (size 1 0.6) (layers "F.Cu") (net 2 "+3V3"))
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(pad "2" smd rect (at -2 -1) (size 1 0.6) (layers "F.Cu") (net 1 "GND"))
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(pad "3" smd rect (at 2 1) (size 1 0.6) (layers "F.Cu") (net 3 "USB_DP"))
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)
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(footprint "Capacitor_SMD:C_0603"
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(layer "F.Cu")
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(at 40 30 0)
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(property "Reference" "C1" (at 0 0 0) (effects (font (size 1 1))))
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(pad "1" smd rect (at -0.5 0) (size 0.8 0.9) (layers "F.Cu") (net 2 "+3V3"))
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(pad "2" smd rect (at 0.5 0) (size 0.8 0.9) (layers "F.Cu") (net 1 "GND"))
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)
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(segment (start 18 11) (end 19 11) (width 0.2) (layer "F.Cu") (net 2))
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)
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"""
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def test_parse_footprints_with_few_tracks(tmp_path: Path):
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p = tmp_path / "partial.kicad_pcb"
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p.write_text(_PARTIAL)
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g = parse_kicad_pcb(p)
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assert "U1" in g.footprints and "C1" in g.footprints
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assert len(g.segments) == 1
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assert g.segments[0].net == "+3V3"
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assert len(g.vias) == 0
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def _partial_graph() -> DesignGraph:
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return DesignGraph(
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components={
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"U1": Component(
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reference="U1", value="MCU", footprint="",
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component_type=ComponentType.IC, mpn="X",
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pins={"1": "+3V3", "2": "GND", "3": "USB_DP"},
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),
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"C1": Component(
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reference="C1", value="100n", footprint="",
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component_type=ComponentType.CAPACITOR, mpn="C",
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pins={"1": "+3V3", "2": "GND"},
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),
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"R9": Component(
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reference="R9", value="10k", footprint="",
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component_type=ComponentType.RESISTOR, mpn="R",
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pins={"1": "NRESET"},
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),
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},
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nets={
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"+3V3": Net(name="+3V3", net_type=NetType.POWER, pins=[]),
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"GND": Net(name="GND", net_type=NetType.GROUND, pins=[]),
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"USB_DP": Net(name="USB_DP", net_type=NetType.SIGNAL, pins=[]),
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"NRESET": Net(name="NRESET", net_type=NetType.SIGNAL, pins=[]),
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},
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)
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def test_run_pcb_checks_on_partial_layout_does_not_invent_tracks(tmp_path: Path):
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p = tmp_path / "partial.kicad_pcb"
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p.write_text(_PARTIAL)
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layout = parse_kicad_pcb(p)
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graph = _partial_graph()
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findings = run_pcb_checks(graph, {}, layout)
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lay = [f for f in findings if f.rule_id == "PE-LAY-004"]
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assert lay, findings
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assert lay[0].evidence_status == "INSUFFICIENT"
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assert lay[0].status == "INFO"
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assert all(f.rule_id != "PE-PLC-001" for f in findings)
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unplaced = [f for f in findings if f.rule_id == "PE-LAY-002"]
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assert any(f.designator == "R9" for f in unplaced)
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def test_partial_board_via_is_not_a_pad(tmp_path: Path):
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from tests.pcb.test_pcb_via_not_pad import _qfn24_pcb
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layout = parse_kicad_pcb(_qfn24_pcb(tmp_path, board_vias=[(80.0, 80.0, "GND", 1)]))
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u1 = layout.footprints["U1"]
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assert len(u1.pads) == 24
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assert len(layout.vias) == 1
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via = layout.vias[0]
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assert all(abs(p.x - via.x) > 0.01 or abs(p.y - via.y) > 0.01 for p in u1.pads)
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def test_unplaced_ref_is_lay_002_not_invented_xy():
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graph = _partial_graph()
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from backend.periscopex.models import LayoutFootprint, LayoutGraph, LayoutPad
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layout = LayoutGraph(
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footprints={
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"U1": LayoutFootprint(
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reference="U1", x=0, y=0, layer="F.Cu",
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pads=[LayoutPad(number="1", x=0, y=0, net="+3V3")],
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),
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},
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)
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findings = check_pcb_net_match(graph, layout)
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assert any(f.rule_id == "PE-LAY-002" and f.designator == "C1" for f in findings)
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assert check_placement(graph, {}, layout) == [] or all(
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f.evidence_status == "INSUFFICIENT" or f.rule_id != "PE-PLC-001"
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for f in check_placement(graph, {}, layout)
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)
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