michele
8f434ffd31
WROOM lands are not the ESP32 die table (U11). QFN-48 pads 25–48 are not extras when extraction stopped at 1–24 (U12). VQFN is the QFN family (U19 24-QFN 4×4). Real extra signal pads still ERROR.
524 lines
17 KiB
Python
524 lines
17 KiB
Python
"""PE-BOM-011 joins pintable × lib × PCB by name. pin_count is not authority."""
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from __future__ import annotations
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from pathlib import Path
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from backend.periscopex.bom_pcb_check import (
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_is_ep_land,
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check_bom_pcb_datasheet,
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)
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from backend.periscopex.models import (
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Component,
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ComponentConstraints,
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ComponentType,
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DesignGraph,
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LayoutFootprint,
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LayoutGraph,
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LayoutPad,
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PackageInfo,
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Pin,
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)
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from backend.periscopex.parsers_kicad_pcb import parse_kicad_pcb
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_HUB_PCB = Path(
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"/Users/michelebigi/Development/HubAudio/hardware/kicad/HubAudio/HubAudio.kicad_pcb"
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)
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_USB_C_PINS = [
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"A1", "A4", "A5", "A6", "A7", "A8", "A9", "A12",
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"B1", "B4", "B5", "B6", "B7", "B8", "B9", "B12",
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]
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def _usb_c_cons(*, pintable: bool) -> ComponentConstraints:
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pins = [Pin(number=n, name=n) for n in _USB_C_PINS] if pintable else []
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return ComponentConstraints(
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mpn="TYPE-C-31-M-12",
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package_info=PackageInfo(
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base_family="USB", package="USB-C-16P", pin_count=16,
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),
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pintable=pins,
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absolute_maximum_ratings=[],
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rules=[],
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)
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def _j2_graph(pins: dict[str, str] | None = None) -> DesignGraph:
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keys = pins or {n: "SIG" for n in _USB_C_PINS}
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keys.setdefault("SH", "GND")
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return DesignGraph(
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components={
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"J2": Component(
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reference="J2",
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value="USB_C_Receptacle_USB2.0_16P",
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footprint="Connector_USB:USB_C_Receptacle_HRO_TYPE-C-31-M-12",
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component_type=ComponentType.CONNECTOR,
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mpn="TYPE-C-31-M-12",
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pins=keys,
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),
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},
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)
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def _j2_layout() -> LayoutGraph:
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pads = [
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LayoutPad(number=n, x=0, y=0, net="SIG", pinfunction=f"PIN_{n}")
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for n in _USB_C_PINS
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]
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pads.extend(
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LayoutPad(number="SH", x=i, y=0, net="GND", pinfunction="SHIELD_SH")
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for i in range(4)
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)
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return LayoutGraph(
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footprints={
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"J2": LayoutFootprint(
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reference="J2",
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footprint="Connector_USB:USB_C_Receptacle_HRO_TYPE-C-31-M-12",
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x=0, y=0, layer="F.Cu",
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pads=pads,
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),
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},
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)
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def _ids(findings) -> set[str]:
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return {f.rule_id for f in findings}
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def test_a5_b5_are_not_ep():
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assert _is_ep_land("A5", "CC1_A5", pin_count=16) is False
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assert _is_ep_land("B5", "CC2_B5", pin_count=16) is False
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assert _is_ep_land("EP", pin_count=8) is True
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assert _is_ep_land("9", "EP", pin_count=8) is True
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assert _is_ep_land("9", pin_count=8) is True
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assert _is_ep_land("9_1", pin_count=8) is True
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def test_usb_c_pin_count_16_without_pintable_is_not_error():
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"""The 16 vs 1 SH false ERROR: pin_count alone must not fire PE-BOM-011."""
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findings = check_bom_pcb_datasheet(
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_j2_graph(), {"TYPE-C-31-M-12": _usb_c_cons(pintable=False)}, _j2_layout(),
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)
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assert "PE-BOM-011" not in _ids(findings)
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assert not any("pin_count=16" in (f.finding or "") for f in findings)
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def test_usb_c_pintable_matches_contacts_ignores_sh_and_mount():
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findings = check_bom_pcb_datasheet(
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_j2_graph(), {"TYPE-C-31-M-12": _usb_c_cons(pintable=True)}, _j2_layout(),
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)
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assert "PE-BOM-011" not in _ids(findings)
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def test_hubaudio_j2_is_not_16_vs_1_signal_pad():
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if not _HUB_PCB.is_file():
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return
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layout = parse_kicad_pcb(_HUB_PCB)
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j2 = layout.footprints.get("J2")
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assert j2 is not None
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numbers = {p.number for p in j2.pads}
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assert "A5" in numbers and "B5" in numbers
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assert "SH" in numbers
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slim = LayoutGraph(footprints={"J2": j2})
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findings = check_bom_pcb_datasheet(
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_j2_graph(), {"TYPE-C-31-M-12": _usb_c_cons(pintable=False)}, slim,
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)
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bom011 = [f for f in findings if f.rule_id == "PE-BOM-011"]
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assert bom011 == []
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findings_named = check_bom_pcb_datasheet(
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_j2_graph(), {"TYPE-C-31-M-12": _usb_c_cons(pintable=True)}, slim,
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)
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assert "PE-BOM-011" not in _ids(findings_named)
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def test_qfn_ep_still_excluded_from_join():
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cons = ComponentConstraints(
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mpn="SW",
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package_info=PackageInfo(base_family="TI", package="SON-8-EP", pin_count=8),
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pintable=[Pin(number=str(i), name=f"P{i}") for i in range(1, 9)],
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absolute_maximum_ratings=[],
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rules=[],
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)
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pads = [LayoutPad(number=str(i), x=0, y=0, net="GND") for i in range(1, 9)]
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pads += [
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LayoutPad(number="9", x=0, y=0, net="GND", pinfunction="EP"),
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LayoutPad(number="9_1", x=0.2, y=0, net="GND"),
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LayoutPad(number="9_2", x=0.4, y=0, net="GND"),
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]
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graph = DesignGraph(
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components={
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"U1": Component(
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reference="U1", value="SW", footprint="SON-8",
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component_type=ComponentType.IC, mpn="SW",
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pins={str(i): "GND" for i in range(1, 9)},
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),
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},
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)
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layout = LayoutGraph(
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footprints={"U1": LayoutFootprint(reference="U1", x=0, y=0, pads=pads)},
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)
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assert "PE-BOM-011" not in _ids(
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check_bom_pcb_datasheet(graph, {"SW": cons}, layout),
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)
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def test_missing_signal_pad_still_fires():
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cons = ComponentConstraints(
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mpn="IC24",
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package_info=PackageInfo(base_family="QFN", package="QFN-24", pin_count=24),
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pintable=[Pin(number=str(i), name=f"P{i}") for i in range(1, 25)],
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absolute_maximum_ratings=[],
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rules=[],
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)
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pads = [LayoutPad(number=str(i), x=0, y=0, net="SIG") for i in range(1, 24)]
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graph = DesignGraph(
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components={
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"U1": Component(
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reference="U1", value="IC", footprint="QFN-24",
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component_type=ComponentType.IC, mpn="IC24",
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pins={str(i): "SIG" for i in range(1, 25)},
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),
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},
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)
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layout = LayoutGraph(
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footprints={"U1": LayoutFootprint(reference="U1", x=0, y=0, pads=pads)},
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)
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findings = check_bom_pcb_datasheet(graph, {"IC24": cons}, layout)
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assert "PE-BOM-011" in _ids(findings)
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assert any("24" in (f.finding or "") for f in findings if f.rule_id == "PE-BOM-011")
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def _write_mod(root: Path, lib: str, name: str, pads: list[str]) -> Path:
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pretty = root / f"{lib}.pretty"
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pretty.mkdir(parents=True, exist_ok=True)
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body = [f'(footprint "{lib}:{name}" (version 20240108) (layer "F.Cu")\n']
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for i, n in enumerate(pads):
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body.append(
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f' (pad "{n}" smd rect (at {i} 0) (size 0.3 0.8) '
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f'(layers "F.Cu" "F.Paste" "F.Mask") (pinfunction "{n}"))\n'
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)
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body.append(")\n")
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path = pretty / f"{name}.kicad_mod"
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path.write_text("".join(body))
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return path
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def test_lib_vs_datasheet_is_lib_finding_not_pcb_pad_count(tmp_path: Path):
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_write_mod(tmp_path, "Pkg", "QFN-8", [str(i) for i in range(1, 8)])
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cons = ComponentConstraints(
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mpn="IC8",
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package_info=PackageInfo(base_family="QFN", package="QFN-8", pin_count=8),
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pintable=[Pin(number=str(i), name=f"P{i}") for i in range(1, 9)],
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absolute_maximum_ratings=[],
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rules=[],
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)
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pads = [LayoutPad(number=str(i), x=0, y=0, net="SIG") for i in range(1, 9)]
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graph = DesignGraph(
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components={
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"U1": Component(
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reference="U1", value="IC", footprint="Pkg:QFN-8",
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component_type=ComponentType.IC, mpn="IC8",
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pins={str(i): "SIG" for i in range(1, 9)},
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),
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},
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)
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layout = LayoutGraph(
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footprints={
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"U1": LayoutFootprint(
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reference="U1", footprint="Pkg:QFN-8", x=0, y=0, pads=pads,
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),
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},
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)
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findings = [
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f for f in check_bom_pcb_datasheet(
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graph, {"IC8": cons}, layout, footprint_dirs=[tmp_path],
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)
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if f.rule_id == "PE-BOM-011"
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]
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assert findings
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text = " ".join(f.finding for f in findings)
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assert "library" in text.lower()
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assert "pin_count=" not in text
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assert "signal pads=" not in text
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def test_lib_vs_embedded_pcb_is_separate_finding(tmp_path: Path):
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_write_mod(tmp_path, "Pkg", "QFN-8", [str(i) for i in range(1, 9)])
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cons = ComponentConstraints(
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mpn="IC8",
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package_info=PackageInfo(base_family="QFN", package="QFN-8", pin_count=8),
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pintable=[Pin(number=str(i), name=f"P{i}") for i in range(1, 9)],
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absolute_maximum_ratings=[],
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rules=[],
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)
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pads = [LayoutPad(number=str(i), x=0, y=0, net="SIG") for i in range(1, 8)]
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pads.append(LayoutPad(number="99", x=1, y=0, net="SIG"))
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graph = DesignGraph(
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components={
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"U1": Component(
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reference="U1", value="IC", footprint="Pkg:QFN-8",
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component_type=ComponentType.IC, mpn="IC8",
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pins={str(i): "SIG" for i in range(1, 9)},
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),
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},
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)
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layout = LayoutGraph(
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footprints={
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"U1": LayoutFootprint(
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reference="U1", footprint="Pkg:QFN-8", x=0, y=0, pads=pads,
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),
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},
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)
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findings = [
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f for f in check_bom_pcb_datasheet(
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graph, {"IC8": cons}, layout, footprint_dirs=[tmp_path],
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)
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if f.rule_id == "PE-BOM-011"
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]
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assert any("embedded" in f.finding.lower() or "PCB" in f.finding for f in findings)
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def _ic(
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ref: str,
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mpn: str,
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footprint: str,
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n_sch: int,
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) -> Component:
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return Component(
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reference=ref, value=mpn, footprint=footprint,
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component_type=ComponentType.IC, mpn=mpn,
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pins={str(i): "SIG" for i in range(1, n_sch + 1)},
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)
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def test_wroom_module_pads_vs_die_pintable_not_bom_011():
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"""U11: WROOM land ≠ ESP32 die 61-pin pintable."""
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cons = ComponentConstraints(
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mpn="ESP32-S31-WROOM-3",
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package_info=PackageInfo(
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base_family="ESP", package="QFN-56", pin_count=61,
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),
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pintable=[Pin(number=str(i), name=f"P{i}") for i in range(1, 62)],
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absolute_maximum_ratings=[],
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rules=[],
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)
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pads = [LayoutPad(number=str(i), x=0, y=0, net="SIG") for i in range(1, 100)]
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graph = DesignGraph(
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components={
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"U11": _ic(
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"U11", "ESP32-S31-WROOM-3",
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"MIKILAB_ESP32_S31_WROOM_3:ESP32-S31-WROOM-3", 41,
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),
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},
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)
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layout = LayoutGraph(
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footprints={
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"U11": LayoutFootprint(
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reference="U11",
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footprint="MIKILAB_ESP32_S31_WROOM_3:ESP32-S31-WROOM-3",
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x=0, y=0, pads=pads,
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),
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},
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)
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ids = _ids(check_bom_pcb_datasheet(graph, {"ESP32-S31-WROOM-3": cons}, layout))
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assert "PE-BOM-011" not in ids
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def test_wroom_missing_die_pin_still_fires():
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cons = ComponentConstraints(
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mpn="ESP32-S31-WROOM-3",
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package_info=PackageInfo(
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base_family="ESP", package="QFN-56", pin_count=61,
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),
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pintable=[Pin(number=str(i), name=f"P{i}") for i in range(1, 62)],
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absolute_maximum_ratings=[],
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rules=[],
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)
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pads = [LayoutPad(number=str(i), x=0, y=0, net="SIG") for i in range(1, 60)]
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graph = DesignGraph(
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components={
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"U11": _ic(
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"U11", "ESP32-S31-WROOM-3",
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"MIKILAB_ESP32_S31_WROOM_3:ESP32-S31-WROOM-3", 40,
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),
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},
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)
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layout = LayoutGraph(
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footprints={
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"U11": LayoutFootprint(
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reference="U11",
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footprint="MIKILAB_ESP32_S31_WROOM_3:ESP32-S31-WROOM-3",
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x=0, y=0, pads=pads,
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),
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},
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)
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assert "PE-BOM-011" in _ids(
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check_bom_pcb_datasheet(graph, {"ESP32-S31-WROOM-3": cons}, layout),
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)
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def test_qfn48_truncated_pintable_24_not_extra_error():
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"""U12: pintable 1–24 vs QFN-48 lands is extraction, not a wrong footprint."""
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cons = ComponentConstraints(
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mpn="Si4684-A10-GM",
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package_info=PackageInfo(
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base_family="Skyworks", package="QFN-48", pin_count=24,
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),
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pintable=[Pin(number=str(i), name=f"P{i}") for i in range(1, 25)],
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absolute_maximum_ratings=[],
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rules=[],
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)
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pads = [LayoutPad(number=str(i), x=0, y=0, net="SIG") for i in range(1, 49)]
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pads.append(LayoutPad(number="49", x=0, y=0, net="GND", pinfunction="EP"))
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graph = DesignGraph(
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components={
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"U12": _ic(
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"U12", "Si4684-A10-GM",
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"Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.3x5.3mm_ThermalVias",
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48,
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),
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},
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)
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layout = LayoutGraph(
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footprints={
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"U12": LayoutFootprint(
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reference="U12",
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footprint="Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.3x5.3mm_ThermalVias",
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x=0, y=0, pads=pads,
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),
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},
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)
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assert "PE-BOM-011" not in _ids(
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check_bom_pcb_datasheet(graph, {"Si4684-A10-GM": cons}, layout),
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)
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def test_qfn24_extra_pad_30_still_fires():
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cons = ComponentConstraints(
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mpn="IC24",
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package_info=PackageInfo(base_family="QFN", package="QFN-24", pin_count=24),
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pintable=[Pin(number=str(i), name=f"P{i}") for i in range(1, 25)],
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absolute_maximum_ratings=[],
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rules=[],
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)
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pads = [LayoutPad(number=str(i), x=0, y=0, net="SIG") for i in range(1, 25)]
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pads.append(LayoutPad(number="30", x=1, y=0, net="SIG"))
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graph = DesignGraph(
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components={"U1": _ic("U1", "IC24", "Package_DFN_QFN:QFN-24-1EP", 24)},
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)
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layout = LayoutGraph(
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footprints={
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"U1": LayoutFootprint(
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reference="U1", footprint="Package_DFN_QFN:QFN-24-1EP",
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x=0, y=0, pads=pads,
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),
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},
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)
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assert "PE-BOM-011" in _ids(
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check_bom_pcb_datasheet(graph, {"IC24": cons}, layout),
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)
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def test_qfn_vs_vqfn_same_24_qfn_land_not_bom_010():
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"""U19: datasheet QFN vs CAD VQFN-24 4×4 is the same land family."""
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cons = ComponentConstraints(
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mpn="LAN8720A",
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package_info=PackageInfo(
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base_family="SMS", package="QFN-24", pin_count=24,
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),
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pintable=[Pin(number=str(i), name=f"P{i}") for i in range(1, 25)],
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absolute_maximum_ratings=[],
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rules=[],
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)
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pads = [LayoutPad(number=str(i), x=0, y=0, net="SIG") for i in range(1, 25)]
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pads.append(LayoutPad(number="25", x=0, y=0, net="GND", pinfunction="EP"))
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graph = DesignGraph(
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components={
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"U19": _ic(
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"U19", "LAN8720A",
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"Package_DFN_QFN:VQFN-24-1EP_4x4mm_P0.5mm_EP2.5x2.5mm_ThermalVias",
|
||
24,
|
||
),
|
||
},
|
||
schematic_fields={
|
||
"U19": {
|
||
"footprint": (
|
||
"Package_DFN_QFN:VQFN-24-1EP_4x4mm_P0.5mm_EP2.5x2.5mm_ThermalVias"
|
||
),
|
||
},
|
||
},
|
||
bom_fields={"U19": {"footprint": "VQFN-24"}},
|
||
)
|
||
layout = LayoutGraph(
|
||
footprints={
|
||
"U19": LayoutFootprint(
|
||
reference="U19",
|
||
footprint=(
|
||
"Package_DFN_QFN:VQFN-24-1EP_4x4mm_P0.5mm_EP2.5x2.5mm_ThermalVias"
|
||
),
|
||
x=0, y=0, pads=pads,
|
||
),
|
||
},
|
||
)
|
||
ids = _ids(check_bom_pcb_datasheet(graph, {"LAN8720A": cons}, layout))
|
||
assert "PE-BOM-010" not in ids
|
||
assert "PE-BOM-011" not in ids
|
||
|
||
|
||
def test_hubaudio_u11_u12_u19_software_not_error():
|
||
if not _HUB_PCB.is_file():
|
||
return
|
||
layout = parse_kicad_pcb(_HUB_PCB)
|
||
slim = LayoutGraph(
|
||
footprints={k: layout.footprints[k] for k in ("U11", "U12", "U19")
|
||
if k in layout.footprints},
|
||
)
|
||
graph = DesignGraph(
|
||
components={
|
||
"U11": _ic(
|
||
"U11", "ESP32-S31-WROOM-3",
|
||
"MIKILAB_ESP32_S31_WROOM_3:ESP32-S31-WROOM-3", 61,
|
||
),
|
||
"U12": _ic(
|
||
"U12", "Si4684-A10-GM",
|
||
"Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.3x5.3mm_ThermalVias",
|
||
48,
|
||
),
|
||
"U19": _ic(
|
||
"U19", "LAN8720A",
|
||
"Package_DFN_QFN:VQFN-24-1EP_4x4mm_P0.5mm_EP2.5x2.5mm_ThermalVias",
|
||
24,
|
||
),
|
||
},
|
||
)
|
||
cmap = {
|
||
"ESP32-S31-WROOM-3": ComponentConstraints(
|
||
mpn="ESP32-S31-WROOM-3",
|
||
package_info=PackageInfo(base_family="ESP", package="QFN-56", pin_count=61),
|
||
pintable=[Pin(number=str(i), name=f"P{i}") for i in range(1, 62)],
|
||
absolute_maximum_ratings=[],
|
||
rules=[],
|
||
),
|
||
"Si4684-A10-GM": ComponentConstraints(
|
||
mpn="Si4684-A10-GM",
|
||
package_info=PackageInfo(base_family="Sky", package="QFN-48", pin_count=24),
|
||
pintable=[Pin(number=str(i), name=f"P{i}") for i in range(1, 25)],
|
||
absolute_maximum_ratings=[],
|
||
rules=[],
|
||
),
|
||
"LAN8720A": ComponentConstraints(
|
||
mpn="LAN8720A",
|
||
package_info=PackageInfo(base_family="SMS", package="QFN-24", pin_count=24),
|
||
pintable=[Pin(number=str(i), name=f"P{i}") for i in range(1, 25)],
|
||
absolute_maximum_ratings=[],
|
||
rules=[],
|
||
),
|
||
}
|
||
findings = check_bom_pcb_datasheet(graph, cmap, slim)
|
||
err = [
|
||
f for f in findings
|
||
if f.rule_id in {"PE-BOM-010", "PE-BOM-011"} and f.status == "ERROR"
|
||
]
|
||
assert err == [], [f.finding for f in err]
|