Commit Graph
23 Commits
Author SHA1 Message Date
micheleandCursor c5b260b404 Prefer .kicad_pcb pad nets when building the design graph.
Schematic geometry on KiCad 10 boards was swapping rails and inventing
floating pins; board connectivity is authoritative when a PCB is uploaded.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-11 12:39:49 +02:00
micheleandCursor a1a2b2a944 Fix KiCad .kicad_sch power/label net merging.
Disconnected GND power flags were named GND_/GND__/… so the reviewer
flagged swapped rails and floating pins on correctly wired designs.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-11 12:15:41 +02:00
micheleandCursor aebe8f6cc3 Accept a KiCad project zip as the upload unit for hierarchical sheets.
Sheets, optional BOM, and PCB are extracted together; a storage round-trip test proves the pipeline can re-parse child Sheetfiles.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-11 08:15:00 +02:00
micheleandCursor 14fd3ba890 Show BOM, schematic, and PCB as three upload boxes on the first wizard screen.
The extra board step made the flow look like only two files were required.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-11 07:48:28 +02:00
micheleandCursor a56dda2358 Accept a KiCad project drop so hierarchical sheets and the board upload in one step.
A single .kicad_sch was parsed in isolation, so child sheets looked like an empty netlist. Report 404s now surface the real API error instead of a generic fetch failure.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-11 07:26:27 +02:00
micheleandCursor 3f6082ae6d Run ImpedenceFinder Z0 on routed signal nets during project analysis.
Pipeline samples PCB traces when stackup εr/h is present; power/ground are skipped. Named nets can be re-analyzed from the Impedance tab.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-11 00:21:49 +02:00
micheleandCursor 796cd9d8a2 Flag keepout tracks in the courtyard and mark the plan map OK.
PS-PLC-004 is a foreign net endpoint inside the KiCad courtyard. The lista↔codice table and sprints 0–10+ get an OK column where the hole is closed without invented millimetres.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-11 00:11:02 +02:00
micheleandCursor 412c32e9b2 Measure crystal load-cap and track path against max_distance_mm.
X1 uses the same proximity rule as ICs. A detour is shortest path on PCB segments versus that millimetre, not a guessed loop ratio.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 23:59:01 +02:00
micheleandCursor ba2a5c1b29 Warn when same_layer decoupling is on the opposite copper.
PS-PLC-003 uses the same_layer flag plus F/B layers from the PCB. A via in the courtyard is enough; an unset flag skips.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 23:45:59 +02:00
micheleandCursor 0fafbbbb06 Count thermal vias in the courtyard against min_via_count.
Skip without courtyard geometry or a numeric count — no pad-radius default. Tests use simple_project plus explicit coordinates as parameters.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 23:39:05 +02:00
micheleandCursor 45e820fabc Add PCB intra-pair skew only when the datasheet gives millimetres.
PS-SI-001 and decoupling skip without a numeric layout_rule. Tests use simple_project nets, not invented USBPHY boards.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 23:34:57 +02:00
micheleandCursor be0fed7979 Add PCB decoupling-proximity check from datasheet layout_rules.
PS-PLC-001 fires only with a LayoutGraph: 15 mm vs a 2 mm rule is an error, a 1 mm cap is silent, and a null millimetre uses the declared 3 mm default as WARNING.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 23:26:10 +02:00
micheleandCursor de15402309 Add finding review states, ECO export, and a report release signature.
Accepted findings become ECO rows with a required reason; false-positive and wontfix stay off the change list. Pipeline re-runs keep dispositions by finding_id like comments.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 23:21:36 +02:00
micheleandCursor 6fc2ac583d Integrate ImpedenceFinder closed-form Z0 into the project Impedance tab.
Use the vendored Hammerstad-Jensen/Cohn engine for microstrip, stripline, and coupled-diff advice. Skip OpenEMS/pcbnew and refuse CPWG rather than inventing a number.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 23:14:57 +02:00
micheleandCursor 7aed64cae5 Add lifecycle, errata, internal-features, and layout_rules checks.
Cache distributor EOL/NRND/RoHS without inventing replacements, flag catalogued errata pull-ups only, and store layout_rules with a closed kind enum so millimetres stay null unless the datasheet stated a number.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 22:48:27 +02:00
micheleandCursor aa375349bd Add KiCad cad-bridge JSON and an action plugin for finding focus.
Write pinscope-findings.json from the report, keep symbol uuid and child-sheet on the graph, and let the pcbnew plugin jump to a footprint or show the schematic uuid when IPC focus is unavailable.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 22:40:28 +02:00
micheleandCursor 78013bd404 Add power-margin, PG-to-EN sequencing, and DNP enable checks.
Compare only specified IQ plus I_load to Iout_max and series-R drop, flag sequencing only when power_sequence is in specs, and treat DNP as a fitted-variant graph so a missing enable pull is ERROR only when the BOM actually marks DNP.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 22:34:06 +02:00
micheleandCursor a45a06e761 Add schematic filter topology and LDO/resistor thermal checks.
Match RC/LC/π/T without inventing fc, compare to ADC rate only when specs list it, and skip ferrite DCR unless the IC gives a limit. LDO Tj uses I_load not Iout_max, and missing θJA stays INFO.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 22:28:40 +02:00
micheleandCursor 4403c38d96 Add DC-bias C_eff stima to derating and INFO when bulk C has no HF ceramic.
Keep both as labelled estimates: no Murata lot curve and no invented Z(f) target without f_sw.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 22:23:05 +02:00
micheleandCursor 4fca789517 Size I2C pull-ups, flag NRST pull-downs, and distinguish LDO Cout from MCU decoupling.
Keep these as WARNING hints with wide bounds so a 4.7 kΩ or 100 nF VDD cap is not treated as a datasheet µF error.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 22:07:14 +02:00
micheleandCursor 61f85f519b Default to DeepSeek V4.1 Flash, show API cost in USD, and re-analyze after replacing BOM and netlist.
V4.1 is natively multimodal so every stage uses deepseek-flash; pricing and the UI now surface dollars instead of empty credits. KiCad netlists and neighborhood fingerprints land in the same cut so a second run can keep the project and skip unchanged ICs.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 20:55:35 +02:00
Cursor Agent 48246f31bd Adapt Pinscope to DeepSeek, auto datasheets, and a shared library.
Based on manvalan/pinscope main. Default LLM is DeepSeek with local
skills and PDF ingest. Datasheets are fetched from LCSC/TI, stored in
the component library, and review extracts abs-max with a deeper
checklist. Adds scripts/update-pinscope.sh for the production host.
2026-08-27 23:06:23 +00:00
Siddharth Kothari 6672d2be57 Pinscope open-source core
Agentic schematic validation: datasheet extraction via Claude Console
Skills, netlist/BOM design graph, per-IC direct datasheet review with
page citations, capacitor derating, Next.js report UI.

Extracted from the Pinscope cloud codebase. Auth and billing live in the
private gateway repo behind stable seams (billing_hook.py, adapter files
listed in CLAUDE.md).
2026-07-16 21:29:45 -07:00