michele/periscope
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aebe8f6cc3b01166bc925031e7a61b01c83e35bc
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7 Commits
Author SHA1 Message Date
micheleandCursor 45e820fabc Add PCB intra-pair skew only when the datasheet gives millimetres. 
PS-SI-001 and decoupling skip without a numeric layout_rule. Tests use simple_project nets, not invented USBPHY boards.

Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-09-10 23:34:57 +02:00
micheleandCursor be0fed7979 Add PCB decoupling-proximity check from datasheet layout_rules. 
PS-PLC-001 fires only with a LayoutGraph: 15 mm vs a 2 mm rule is an error, a 1 mm cap is silent, and a null millimetre uses the declared 3 mm default as WARNING.

Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-09-10 23:26:10 +02:00
micheleandCursor 7aed64cae5 Add lifecycle, errata, internal-features, and layout_rules checks. 
Cache distributor EOL/NRND/RoHS without inventing replacements, flag catalogued errata pull-ups only, and store layout_rules with a closed kind enum so millimetres stay null unless the datasheet stated a number.

Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-09-10 22:48:27 +02:00
micheleandCursor 78013bd404 Add power-margin, PG-to-EN sequencing, and DNP enable checks. 
Compare only specified IQ plus I_load to Iout_max and series-R drop, flag sequencing only when power_sequence is in specs, and treat DNP as a fitted-variant graph so a missing enable pull is ERROR only when the BOM actually marks DNP.

Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-09-10 22:34:06 +02:00
micheleandCursor a45a06e761 Add schematic filter topology and LDO/resistor thermal checks. 
Match RC/LC/π/T without inventing fc, compare to ADC rate only when specs list it, and skip ferrite DCR unless the IC gives a limit. LDO Tj uses I_load not Iout_max, and missing θJA stays INFO.

Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-09-10 22:28:40 +02:00
micheleandCursor 4403c38d96 Add DC-bias C_eff stima to derating and INFO when bulk C has no HF ceramic. 
Keep both as labelled estimates: no Murata lot curve and no invented Z(f) target without f_sw.

Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-09-10 22:23:05 +02:00
micheleandCursor e4fd6c3849 Ship Sprint 0 CAD foundations so findings, KiCad hierarchy, BOM match, eval, and optional PCB ingest have a stable contract. 
Extend Finding with rule_id/net/pins, flatten multi-sheet .kicad_sch, flag MPN mismatches, score simple_project, and parse .kicad_pcb without running layout DRC.

Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-09-10 21:54:37 +02:00