michele/periscope
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2 Commits
Author SHA1 Message Date
michele 69d5dd9313 Add HF line and bus analysis to run_pcb_checks (2.62.0). 
Phase A: stub, return-split, and BOM termination on buses present on the
graph; DDR/CPU/FPGA class certifiers only when that device exists. Skip
without evidence. Via, pad, track, and zone stay distinct. Not DRC or FEM.
 2026-09-21 20:42:55 +02:00
michele 7d82358e19 Rewrite project file drop zone. 
Folder drops still skip KiCad backups/pretty/3dmodels; dashed upload chrome is unchanged.
 2026-09-20 20:11:48 +02:00