michele/periscope
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342792df2dafe7ae425b271bc63da0bc2d750789
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5 Commits
Author SHA1 Message Date
michele 342792df2d Ship Fase B slices: hierarchy, derating bands, timing, PI, ESD/return. 
ERROR stays only for RULE+MANDATORY. Hierarchy walks component→pin→net→block.
Derating is PASS/MARGIN/RISK from Vop/Vrated. Timing and PI skip without numbers.
ESD and HS return path are REVIEW, not RULE ERROR.
 2026-09-20 09:35:04 +02:00
michele 1e379f6042 Restore build_placement_plan import in the PCB pipeline. 
MODE=pcb classify crashed with NameError after the finding-engine import swap.
 2026-09-20 08:44:26 +02:00
michele dc65e96a22 Apply the finding engine to schematic and PCB reviews. 
FACT, REQUIREMENT, and INFERENCE are separate fields; datasheet provenance
lives in the rule DB so Recommended cannot stay ERROR; LLM output is REVIEW.
Designer decisions persist across rescans. Schematic and PCB share one library
and the same finding object in the report UI.
 2026-09-20 08:38:59 +02:00
michele 8f4ebc645c Share library/extracted for schematic and PCB review. 
PCB AI skips a second PDF exam (pintable cache, pdf_path=None) and the report
gains a PCB exam section plus power-trace, thermal, via, Kelvin, and GND-stitch
checks grounded in board geometry and extracted specs.
 2026-09-20 08:32:23 +02:00
michele 16c606ae3d Add MODE=pcb layout exam job with AI and deterministic checks. 
Parallel pcb_status pipeline: parse board, classify domains/groups,
inventory traces, PE-LAY/PLC/SI/DRT checks, per-IC datasheet review.
Findings merge into the report UI. No auto-place or pcbnew write-back.
 2026-09-19 22:54:17 +02:00