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342792df2dafe7ae425b271bc63da0bc2d750789
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8 Commits
Author SHA1 Message Date
michele 342792df2d Ship Fase B slices: hierarchy, derating bands, timing, PI, ESD/return. 
ERROR stays only for RULE+MANDATORY. Hierarchy walks component→pin→net→block.
Derating is PASS/MARGIN/RISK from Vop/Vrated. Timing and PI skip without numbers.
ESD and HS return path are REVIEW, not RULE ERROR.
 2026-09-20 09:35:04 +02:00
michele facbaa2305 Show Action on finding cards and inject PCB geometry into AI context. 
Layout and AI findings always get action (fallback recommendation). The card
renders that sentence in the body. PCB review context now includes vias under
the footprint, copper thickness, nearby widths, courtyard, and keepout polygons.
 2026-09-20 09:13:51 +02:00
michele f63c1c3411 Tighten PCB findings: actions, stitch gating, real copper. 
Fill action on every finding and show it in the report. Stitch/return only
on large HS/power nets. Parse stackup thickness, arcs, and vias from the
board. IC courtyard pad copper is not PE-PLC-004 RULE. Recommended RC/cap
stay REVIEW.
 2026-09-20 08:58:54 +02:00
michele dc65e96a22 Apply the finding engine to schematic and PCB reviews. 
FACT, REQUIREMENT, and INFERENCE are separate fields; datasheet provenance
lives in the rule DB so Recommended cannot stay ERROR; LLM output is REVIEW.
Designer decisions persist across rescans. Schematic and PCB share one library
and the same finding object in the report UI.
 2026-09-20 08:38:59 +02:00
michele 8f4ebc645c Share library/extracted for schematic and PCB review. 
PCB AI skips a second PDF exam (pintable cache, pdf_path=None) and the report
gains a PCB exam section plus power-trace, thermal, via, Kelvin, and GND-stitch
checks grounded in board geometry and extracted specs.
 2026-09-20 08:32:23 +02:00
michele f3f96ea4d1 Treat KiCad /net vs schematic net as one hierarchy finding. 
Pad-net compare strips leading slash and nested sheet path so /ESP32_EN
matches ESP32_EN. If every mismatch is only that prefix, emit PE-LAY-003
once instead of per-pad reconnect errors.
 2026-09-20 08:10:34 +02:00
michele 16c606ae3d Add MODE=pcb layout exam job with AI and deterministic checks. 
Parallel pcb_status pipeline: parse board, classify domains/groups,
inventory traces, PE-LAY/PLC/SI/DRT checks, per-IC datasheet review.
Findings merge into the report UI. No auto-place or pcbnew write-back.
 2026-09-19 22:54:17 +02:00
micheleandCursor 8d2b85600f Rebrand Pinscope to Periscope across product and codebase. 
Rename the core package to periscopex, update UI/docs/Docker/deploy defaults to periscope.michelebigi.it, and keep legacy version/storage key aliases so existing projects keep working.

Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-09-13 20:02:04 +02:00