michele/periscope
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
77 Commits 8 Branches 1 Tag
21e2be1cd037a8a74f8fd3d65a9d4e084d5b9e88
Commit Graph
4 Commits
Author SHA1 Message Date
micheleandCursor c5b260b404 Prefer .kicad_pcb pad nets when building the design graph. 
Schematic geometry on KiCad 10 boards was swapping rails and inventing
floating pins; board connectivity is authoritative when a PCB is uploaded.

Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-09-11 12:39:49 +02:00
micheleandCursor 3f6082ae6d Run ImpedenceFinder Z0 on routed signal nets during project analysis. 
Pipeline samples PCB traces when stackup εr/h is present; power/ground are skipped. Named nets can be re-analyzed from the Impedance tab.

Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-09-11 00:21:49 +02:00
micheleandCursor 0fafbbbb06 Count thermal vias in the courtyard against min_via_count. 
Skip without courtyard geometry or a numeric count — no pad-radius default. Tests use simple_project plus explicit coordinates as parameters.

Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-09-10 23:39:05 +02:00
micheleandCursor e4fd6c3849 Ship Sprint 0 CAD foundations so findings, KiCad hierarchy, BOM match, eval, and optional PCB ingest have a stable contract. 
Extend Finding with rule_id/net/pins, flatten multi-sheet .kicad_sch, flag MPN mismatches, score simple_project, and parse .kicad_pcb without running layout DRC.

Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-09-10 21:54:37 +02:00