Commit Graph
6 Commits
Author SHA1 Message Date
micheleandCursor 796cd9d8a2 Flag keepout tracks in the courtyard and mark the plan map OK.
PS-PLC-004 is a foreign net endpoint inside the KiCad courtyard. The lista↔codice table and sprints 0–10+ get an OK column where the hole is closed without invented millimetres.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-11 00:11:02 +02:00
micheleandCursor 412c32e9b2 Measure crystal load-cap and track path against max_distance_mm.
X1 uses the same proximity rule as ICs. A detour is shortest path on PCB segments versus that millimetre, not a guessed loop ratio.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 23:59:01 +02:00
micheleandCursor ba2a5c1b29 Warn when same_layer decoupling is on the opposite copper.
PS-PLC-003 uses the same_layer flag plus F/B layers from the PCB. A via in the courtyard is enough; an unset flag skips.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 23:45:59 +02:00
micheleandCursor 0fafbbbb06 Count thermal vias in the courtyard against min_via_count.
Skip without courtyard geometry or a numeric count — no pad-radius default. Tests use simple_project plus explicit coordinates as parameters.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 23:39:05 +02:00
micheleandCursor 45e820fabc Add PCB intra-pair skew only when the datasheet gives millimetres.
PS-SI-001 and decoupling skip without a numeric layout_rule. Tests use simple_project nets, not invented USBPHY boards.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 23:34:57 +02:00
micheleandCursor be0fed7979 Add PCB decoupling-proximity check from datasheet layout_rules.
PS-PLC-001 fires only with a LayoutGraph: 15 mm vs a 2 mm rule is an error, a 1 mm cap is silent, and a null millimetre uses the declared 3 mm default as WARNING.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 23:26:10 +02:00