Tighten PCB findings: actions, stitch gating, real copper.
Fill action on every finding and show it in the report. Stitch/return only on large HS/power nets. Parse stackup thickness, arcs, and vias from the board. IC courtyard pad copper is not PE-PLC-004 RULE. Recommended RC/cap stay REVIEW.
This commit is contained in:
@@ -18,7 +18,10 @@ Provenance = Literal["MANDATORY", "RECOMMENDED", "TYPICAL", "EXAMPLE"]
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FindingClass = Literal["RULE", "RISK", "REVIEW", "INFO"]
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EvidenceStatus = Literal["SUFFICIENT", "INSUFFICIENT"]
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_LLM_SOURCES = frozenset({None, "review", "pcb_review"})
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_DEFAULT_ACTION = (
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"Review this finding against the datasheet and the board, then change "
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"the design if it applies."
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)
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_SOFT_PROVENANCE = frozenset({"RECOMMENDED", "TYPICAL", "EXAMPLE"})
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@@ -71,17 +74,20 @@ def _seed() -> None:
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("PE-MUX-001", "Pin function must match the mux / datasheet pin table."),
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("PE-NC-001", "NC pins must not be connected."),
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("PE-DEC-001", "Supply pin requires a decoupling capacitor on that net."),
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("PE-DEC-002", "Decoupling capacitor value vs datasheet."),
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("PE-I2C-001", "I2C bus requires pull-ups."),
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("PE-I2C-002", "I2C pull-up value vs datasheet."),
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("PE-RST-001", "Reset pin requires the specified pull."),
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("PE-RST-002", "Reset pull value vs datasheet."),
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("PE-BOM-001", "BOM MPN must match the netlist part."),
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("PE-BOM-002", "BOM line missing from the netlist."),
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("PE-DNP-001", "DNP / fitted state vs netlist."),
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("PE-DRT-001", "Operating voltage must not exceed the capacitor rating."),
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):
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_add(rid, "MANDATORY", "RULE", domain="schema", requirement=req)
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for rid, req in (
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("PE-DEC-002", "Decoupling capacitor value vs datasheet (recommended)."),
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("PE-I2C-002", "I2C pull-up value vs datasheet (recommended)."),
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("PE-RST-002", "Reset pull value vs datasheet (recommended)."),
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):
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_add(rid, "RECOMMENDED", "REVIEW", domain="schema", requirement=req)
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for rid in ("PE-TH-001", "PE-TH-003"):
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_add(rid, "TYPICAL", "RISK", domain="schema",
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requirement="Thermal estimate only with I_load and θJA from specs.")
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@@ -93,12 +99,12 @@ def _seed() -> None:
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requirement="Trace width × copper thickness vs I_load (IPC-2221 when ΔT known).")
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for rid, prov, cls, req in (
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("PE-SEQ-001", "RECOMMENDED", "RISK", "Power sequencing from datasheet notes."),
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("PE-FLT-001", "RECOMMENDED", "RISK", "Filter topology vs datasheet."),
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("PE-FLT-002", "RECOMMENDED", "RISK", "Filter component vs datasheet."),
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("PE-FLT-003", "RECOMMENDED", "RISK", "Filter cutoff vs datasheet."),
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("PE-FLT-001", "RECOMMENDED", "REVIEW", "Filter topology vs datasheet."),
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("PE-FLT-002", "RECOMMENDED", "REVIEW", "Filter component vs datasheet."),
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("PE-FLT-003", "RECOMMENDED", "REVIEW", "Filter cutoff vs datasheet."),
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("PE-XTAL-001", "MANDATORY", "RULE", "Crystal load capacitance vs Cl."),
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("PE-XTAL-002", "RECOMMENDED", "RISK", "Crystal layout / load-cap note."),
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("PE-XTAL-003", "RECOMMENDED", "RISK", "Crystal drive / Cl note."),
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("PE-XTAL-002", "RECOMMENDED", "REVIEW", "Crystal layout / load-cap note."),
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("PE-XTAL-003", "RECOMMENDED", "REVIEW", "Crystal drive / Cl note."),
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("PE-LF-001", "TYPICAL", "INFO", "Lifecycle / NRND."),
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("PE-LF-002", "TYPICAL", "INFO", "Lifecycle / last-time-buy."),
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("PE-LF-003", "TYPICAL", "INFO", "Lifecycle / obsolete."),
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@@ -118,10 +124,11 @@ def _seed() -> None:
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("PE-PLC-001", "Decoupling proximity max_distance_mm from layout_rules."),
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("PE-PLC-002", "Thermal via min_via_count from layout_rules."),
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("PE-PLC-003", "same_layer decoupling from layout_rules."),
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("PE-PLC-004", "Keepout from layout_rules."),
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("PE-SI-001", "Differential skew vs length_match mm."),
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):
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_add(rid, "MANDATORY", "RULE", domain="pcb", requirement=req)
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_add("PE-PLC-004", "RECOMMENDED", "REVIEW", domain="pcb",
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requirement="Keepout from layout_rules — not a DRC for pad copper.")
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_add("PE-VIA-001", "TYPICAL", "INFO", domain="pcb",
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requirement="Via current share from I_load and via count (no invented table).")
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_add("PE-THM-001", "RECOMMENDED", "RISK", domain="pcb",
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@@ -160,8 +167,8 @@ def complete_finding(f: Finding) -> Finding:
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if not (f.requirement or "").strip():
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f.requirement = (rec.requirement if rec and rec.requirement else None) or f.why
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if not (f.action or "").strip():
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f.action = f.recommendation or ""
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if not (f.recommendation or "").strip() and f.action:
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f.action = (f.recommendation or "").strip() or _DEFAULT_ACTION
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if not (f.recommendation or "").strip():
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f.recommendation = f.action
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llm = (f.source in {None, "review", "pcb_review"}) and not f.rule_id
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@@ -219,6 +226,10 @@ def complete_finding(f: Finding) -> Finding:
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f.why = f.requirement
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if not (f.finding or "").strip():
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f.finding = f.facts
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if not (f.action or "").strip():
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f.action = _DEFAULT_ACTION
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if not (f.recommendation or "").strip():
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f.recommendation = f.action
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return f
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@@ -5,6 +5,7 @@ No SI/DRC. Schema validation stays complete without this file.
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from __future__ import annotations
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import re
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from pathlib import Path
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from backend.periscopex.models import (
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@@ -29,6 +30,24 @@ from backend.periscopex.parsers_kicad import (
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)
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def _copper_thickness_token(raw: object) -> float | None:
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"""Parse KiCad stackup thickness; units mm/um/mil. Never default 1 oz."""
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if isinstance(raw, (int, float)) and not isinstance(raw, bool):
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v = float(raw)
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return v if v > 0 else None
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s = str(raw or "").strip().lower().replace(" ", "")
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m = re.match(r"^([0-9]*\.?[0-9]+)(mm|um|µm|mil)?", s)
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if not m:
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return None
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n = float(m.group(1))
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unit = m.group(2) or "mm"
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if unit in {"um", "µm"}:
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n = n / 1000.0
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elif unit == "mil":
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n = n * 0.0254
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return n if n > 0 else None
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def _xy(node: object, name: str) -> tuple[float, float]:
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k = _kid(node, name)
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if not k or len(k) < 3:
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@@ -128,7 +147,11 @@ def _parse_stackup(tree: object) -> LayoutStackup | None:
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name = str(layer[1]) if len(layer) > 1 and not isinstance(layer[1], list) else ""
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kind = _layer_type(layer)
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thick = _kid(layer, "thickness")
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height = _fnum(thick[1]) if thick and len(thick) > 1 else None
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height = None
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if thick and len(thick) > 1:
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height = _copper_thickness_token(thick[1])
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if height is None and len(thick) > 2:
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height = _copper_thickness_token(f"{thick[1]}{thick[2]}")
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if kind == "copper" or name.endswith(".Cu"):
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if name:
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copper.append(name)
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@@ -147,9 +170,9 @@ def _parse_stackup(tree: object) -> LayoutStackup | None:
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er=er,
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height_mm=height,
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))
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if len(copper) < 2 or len(dielectrics) != len(copper) - 1:
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return None
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t = thicknesses[0] if thicknesses else None
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if not copper and t is None:
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return None
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return LayoutStackup(
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copper_layers=copper,
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dielectrics=dielectrics,
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@@ -291,6 +314,15 @@ def parse_kicad_pcb(path: str | Path) -> LayoutGraph:
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net=_net_name(node, nets),
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))
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continue
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if tag == "arc":
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segments.append(LayoutSegment(
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start=_xy(node, "start"),
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end=_xy(node, "end"),
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width=_fnum(_val(node, "width") or 0),
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layer=_val(node, "layer"),
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net=_net_name(node, nets),
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))
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continue
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if tag == "via":
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drill_el = _kid(node, "drill")
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drill = _fnum(drill_el[1]) if drill_el and len(drill_el) > 1 else None
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@@ -37,6 +37,12 @@ _IPC_K_EXT = 0.048
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_IPC_K_INT = 0.024
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_TJMAX_KEYS = ("tj_max", "tj_max_c", "tjmax", "max_junction_temp_c", "t_jmax")
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_SENSE_RE = re.compile(r"(kelvin|sense|isns|i_sns|cs\+|cs-|iout_sns)", re.I)
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_HS_NET_RE = re.compile(
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r"(USB|DP|DM|D\+|D-|HS|HDMI|MIPI|DDR|CLK|XTAL|HFX|LFX|SWP|DIFF)",
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re.I,
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)
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_STITCH_MIN_SPAN_MM = 12.0
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_STITCH_MIN_AREA_MM2 = 40.0
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def _mm_to_mil(mm: float) -> float:
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@@ -75,6 +81,17 @@ def _via_stats(layout: LayoutGraph, sch_net: str) -> tuple[int, float | None]:
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return n, (min(drills) if drills else None)
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def _footprint_region(fp) -> list[tuple[float, float]]:
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if len(fp.courtyard) >= 3:
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return fp.courtyard
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xs = [fp.x] + [p.x for p in fp.pads]
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ys = [fp.y] + [p.y for p in fp.pads]
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pad = 1.5
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xmin, xmax = min(xs) - pad, max(xs) + pad
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ymin, ymax = min(ys) - pad, max(ys) + pad
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return [(xmin, ymin), (xmax, ymin), (xmax, ymax), (xmin, ymax)]
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def _external_layers(layers: list[str]) -> bool:
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if not layers:
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return True
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@@ -223,28 +240,36 @@ def check_pcb_via_current(
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if key in seen:
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continue
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seen.add(key)
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n, drill = _via_stats(layout, net)
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if n <= 0:
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n, _drill = _via_stats(layout, net)
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if n > 0:
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# Geometry is present; no via-ampacity table in the library — do not
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# invent a rating or claim the vias were not parsed.
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continue
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per = i_load / n
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out.append(Finding(
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designator=ref,
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mpn=comp.mpn or "",
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aspect="layout_power",
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finding=(
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f"{net} shares I_load={i_load:.3g} A across {n} via(s) "
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f"(≈{per:.3g} A each"
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+ (f", min drill {drill:g} mm" if drill else "")
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+ "). No via current rating in the library extraction."
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f"{net} carries I_load={i_load:.3g} A with no vias on that net "
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"in the parsed .kicad_pcb."
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),
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why="Via current is reported from board geometry + datasheet I_load only.",
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why="Via count is taken from board vias whose net matches this supply.",
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status="INFO",
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recommendation=(
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"If the datasheet or stackup vendor quotes via current, add more/larger vias "
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f"so each via stays under that rating at {i_load:.3g} A."
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f"Add vias on {net} if the current leaves this layer, then re-run PCB review."
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),
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action=(
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f"Add vias on {net} if the current leaves this layer, then re-run PCB review."
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),
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source="pcb_power_thermal",
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rule_id="PE-VIA-001",
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evidence_status="SUFFICIENT",
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facts=(
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f"I_load={i_load:.3g} A on {net}; 0 vias with a matching net "
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f"in the PCB file (board has {len(layout.vias)} via(s) total)."
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),
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requirement="No datasheet via current; report missing vias only.",
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inference="Ampacity of vias is not judged without a rating.",
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net=net,
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pins=[],
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))
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@@ -276,12 +301,15 @@ def check_pcb_thermal_copper(
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continue
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p = i_load * (vin - vout)
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fp = layout.footprints.get(ref)
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if not fp or len(fp.courtyard) < 3:
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if not fp:
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continue
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region = _footprint_region(fp)
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if len(region) < 3:
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continue
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theta = _first(values, _THETA_KEYS)
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via_n = 0
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for v in layout.vias:
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if _in_poly(v.x, v.y, fp.courtyard):
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if _in_poly(v.x, v.y, region):
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via_n += 1
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pour = False
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for z in layout.zones:
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@@ -296,7 +324,6 @@ def check_pcb_thermal_copper(
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):
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pass
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else:
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# GND by name
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leaf = normalize_kicad_hierarchy_net(z.net).upper()
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if not (leaf == "GND" or leaf.endswith("/GND") or "GND" in leaf):
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continue
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@@ -306,26 +333,39 @@ def check_pcb_thermal_copper(
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break
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if via_n or pour:
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continue
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rec = (
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"Add a copper pour and/or thermal vias under the package as the datasheet "
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"layout page specifies, then re-run PCB review."
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)
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out.append(Finding(
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designator=ref,
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mpn=comp.mpn or "",
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aspect="layout_thermal",
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finding=(
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f"{ref} dissipates ≈{p:.3g} W (I_load={i_load:.3g} A) but the courtyard "
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"has no thermal vias and no overlapping copper pour."
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f"{ref} dissipates ≈{p:.3g} W (I_load={i_load:.3g} A) but the package "
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f"region has no thermal vias ({via_n}) and no overlapping copper pour "
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f"(board vias parsed: {len(layout.vias)})."
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),
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facts=(
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f"P≈{p:.3g} W; {via_n} vias in package region; pour={pour}; "
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f"{len(layout.vias)} vias on the board."
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),
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requirement=(
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"Datasheet layout notes for copper/vias under the package "
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"(recommended, not a shall)."
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),
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inference="No pour/vias under the package on the parsed board.",
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why=(
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"P = I_load×(Vin−Vout) from the shared extraction/specs. "
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+ (f"θJA={theta:.3g} °C/W. " if theta else "θJA missing. ")
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+ "No millimetres invented."
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),
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status="WARNING",
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recommendation=(
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"Add a copper pour and/or thermal vias under the package as the datasheet "
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"layout page specifies, then re-run PCB review."
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),
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recommendation=rec,
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action=rec,
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source="pcb_power_thermal",
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rule_id="PE-THM-001",
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evidence_status="SUFFICIENT" if layout.vias or layout.zones else "INSUFFICIENT",
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net=vout_n,
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pins=[],
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))
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@@ -337,11 +377,24 @@ def _is_gnd_name(name: str) -> bool:
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return leaf in {"GND", "AGND", "DGND", "PGND", "VSS"} or leaf.endswith("/GND")
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def _is_stitch_candidate(net_name: str, net, dx: float, dy: float) -> bool:
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"""High-speed / power nets, or a large bbox — never tiny GPIO stubs."""
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span = max(dx, dy)
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area = dx * dy
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if span < _STITCH_MIN_SPAN_MM or area < _STITCH_MIN_AREA_MM2:
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return False
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if net.net_type == NetType.POWER:
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return True
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if _HS_NET_RE.search(net_name or ""):
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return True
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return False
|
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|
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def check_pcb_gnd_stitch(
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graph: DesignGraph,
|
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layout: LayoutGraph | None,
|
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) -> list[Finding]:
|
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"""INFO when a signal span has a GND pour but no GND via in its bbox."""
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"""INFO when a long HS/power span has a GND pour but no GND via in its bbox."""
|
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if layout is None:
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return []
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gnd_zones = [
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@@ -357,7 +410,7 @@ def check_pcb_gnd_stitch(
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out: list[Finding] = []
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seen: set[str] = set()
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for net_name, net in sorted(graph.nets.items()):
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if net.net_type != NetType.SIGNAL:
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if net.net_type not in (NetType.SIGNAL, NetType.POWER):
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continue
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key = normalize_kicad_hierarchy_net(net_name)
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if key in seen:
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@@ -375,30 +428,39 @@ def check_pcb_gnd_stitch(
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ys.extend([s.start[1], s.end[1]])
|
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xmin, xmax = min(xs), max(xs)
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ymin, ymax = min(ys), max(ys)
|
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if xmax - xmin < 2.0 and ymax - ymin < 2.0:
|
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dx, dy = xmax - xmin, ymax - ymin
|
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if not _is_stitch_candidate(net_name, net, dx, dy):
|
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continue
|
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if any(xmin <= v.x <= xmax and ymin <= v.y <= ymax for v in gnd_vias):
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continue
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seen.add(key)
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refs = [p.component_ref for p in net.pins[:1]]
|
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ref = refs[0] if refs else net_name
|
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rec = (
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f"Add GND stitch vias along '{net_name}' so the return current "
|
||||
"has a nearby via to the ground plane."
|
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)
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out.append(Finding(
|
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designator=ref,
|
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mpn=(graph.components[ref].mpn if ref in graph.components else "") or "",
|
||||
aspect="layout_return",
|
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finding=(
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f"Signal '{net_name}' spans {xmax - xmin:.1f}×{ymax - ymin:.1f} mm "
|
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f"Net '{net_name}' spans {dx:.1f}×{dy:.1f} mm "
|
||||
"over a GND pour with no GND via in that bounding box."
|
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),
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facts=(
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||||
f"BBox {dx:.1f}×{dy:.1f} mm on '{net_name}'; "
|
||||
f"{len(gnd_vias)} GND via(s) on the board, none in bbox."
|
||||
),
|
||||
requirement="Return current needs a nearby GND via on long HS/power routes.",
|
||||
inference="No GND via in the span — stitch if the return path should stay local.",
|
||||
why=(
|
||||
"Return path / stitch vias are inferred from board zones and vias only "
|
||||
"(no IEC clearance invented)."
|
||||
),
|
||||
status="INFO",
|
||||
recommendation=(
|
||||
f"Add GND stitch vias along '{net_name}' so the return current "
|
||||
"has a nearby via to the ground plane."
|
||||
),
|
||||
recommendation=rec,
|
||||
action=rec,
|
||||
source="pcb_power_thermal",
|
||||
rule_id="PE-STCH-001",
|
||||
net=net_name,
|
||||
|
||||
@@ -289,9 +289,15 @@ def _keepout_finding(ref, comp, cons, rule, graph: DesignGraph, layout: LayoutGr
|
||||
own = _net_for_pin(graph, ref, pin_no) if pin_no else None
|
||||
if not own:
|
||||
return []
|
||||
pad_nets = [
|
||||
p.net for p in fp.pads
|
||||
if p.net
|
||||
]
|
||||
foreign: list[str] = []
|
||||
for s in layout.segments:
|
||||
if not s.net or s.net == own:
|
||||
if not s.net or kicad_nets_match(s.net, own):
|
||||
continue
|
||||
if any(kicad_nets_match(s.net, pn) for pn in pad_nets):
|
||||
continue
|
||||
if _in_poly(s.start[0], s.start[1], fp.courtyard) or _in_poly(
|
||||
s.end[0], s.end[1], fp.courtyard
|
||||
@@ -300,17 +306,32 @@ def _keepout_finding(ref, comp, cons, rule, graph: DesignGraph, layout: LayoutGr
|
||||
if not foreign:
|
||||
return []
|
||||
net = sorted(set(foreign))[0]
|
||||
is_crystal = comp.component_type == ComponentType.CRYSTAL
|
||||
rec = (
|
||||
"Keep unrelated nets out of the keepout if the datasheet shows a "
|
||||
"keep-out zone; traces to this part's own pads are normal copper."
|
||||
)
|
||||
return [Finding(
|
||||
designator=ref,
|
||||
mpn=comp.mpn or cons.mpn,
|
||||
aspect="placement",
|
||||
finding=f"Track on {net} enters courtyard of {ref} (keepout on {own}).",
|
||||
facts=f"Segment on '{net}' has an endpoint inside {ref} courtyard.",
|
||||
requirement="layout_rules kind=keepout (recommended courtyard isolation).",
|
||||
inference=(
|
||||
"Crystal keepout may apply."
|
||||
if is_crystal
|
||||
else "Not a pad net of this footprint — review, not a mandatory DRC."
|
||||
),
|
||||
why="layout_rules kind=keepout.",
|
||||
status="WARNING",
|
||||
recommendation="Keep other nets out of the courtyard.",
|
||||
status="WARNING" if is_crystal else "INFO",
|
||||
recommendation=rec,
|
||||
action=rec,
|
||||
source="placement_check",
|
||||
rule_id="PE-PLC-004",
|
||||
finding_class="REVIEW",
|
||||
provenance="RECOMMENDED",
|
||||
net=net,
|
||||
pins=[pin_no],
|
||||
pins=[pin_no] if pin_no else [],
|
||||
source_page=rule.get("source_page"),
|
||||
)]
|
||||
|
||||
@@ -58,8 +58,9 @@ export function FindingCard({
|
||||
const [open, setOpen] = useState(defaultOpen ?? false);
|
||||
const commentCount = comments?.length ?? 0;
|
||||
const hasCommentSupport = !!(projectId && collaborators && onCommentAdded && onCommentDeleted);
|
||||
const actionText = (finding.action || finding.recommendation || "").trim();
|
||||
const expandable =
|
||||
!!finding.recommendation ||
|
||||
!!actionText ||
|
||||
!!finding.facts ||
|
||||
!!finding.requirement ||
|
||||
!!finding.inference ||
|
||||
@@ -116,17 +117,17 @@ export function FindingCard({
|
||||
)}
|
||||
<span>{finding.finding}</span>
|
||||
</p>
|
||||
{finding.why && (
|
||||
{finding.why && !finding.facts && !finding.requirement && (
|
||||
<p className="text-sm text-muted-foreground leading-relaxed">{finding.why}</p>
|
||||
)}
|
||||
|
||||
<div className="flex items-center gap-2 pt-1">
|
||||
{finding.recommendation && (
|
||||
{actionText && (
|
||||
<span className="inline-flex items-center h-7 px-2 text-xs text-muted-foreground">
|
||||
<ChevronDown
|
||||
className={cn("h-3.5 w-3.5 mr-1 transition-transform", open && "rotate-180")}
|
||||
/>
|
||||
Recommendation
|
||||
Action
|
||||
</span>
|
||||
)}
|
||||
{hasCommentSupport && finding.finding_id && (
|
||||
@@ -249,9 +250,10 @@ export function FindingCard({
|
||||
) : null}
|
||||
</dl>
|
||||
)}
|
||||
{finding.recommendation && (
|
||||
{actionText && (
|
||||
<p className="text-sm text-muted-foreground mt-2 pl-1 border-l-2 border-muted leading-relaxed">
|
||||
{finding.recommendation}
|
||||
<span className="font-medium text-foreground">Action. </span>
|
||||
{actionText}
|
||||
</p>
|
||||
)}
|
||||
{hasCommentSupport && finding.finding_id && (
|
||||
|
||||
@@ -133,3 +133,26 @@ def test_same_object_pcb_and_schema():
|
||||
assert obj.finding_class
|
||||
assert obj.provenance
|
||||
assert obj.evidence_status
|
||||
assert (obj.action or "").strip()
|
||||
|
||||
|
||||
def test_empty_recommendation_gets_action():
|
||||
f = Finding(designator="U1", finding="note", status="INFO", source="review")
|
||||
complete_finding(f)
|
||||
assert f.action.strip()
|
||||
assert f.recommendation.strip() == f.action.strip()
|
||||
|
||||
|
||||
def test_recommended_rc_cap_is_review_not_rule():
|
||||
f = Finding(
|
||||
designator="C1",
|
||||
finding="10n vs 100n",
|
||||
why="datasheet typical 100n",
|
||||
status="WARNING",
|
||||
rule_id="PE-DEC-002",
|
||||
source="passive_rail_check",
|
||||
)
|
||||
complete_finding(f)
|
||||
assert f.finding_class == "REVIEW"
|
||||
assert f.provenance == "RECOMMENDED"
|
||||
assert f.status != "ERROR"
|
||||
|
||||
@@ -237,3 +237,25 @@ def test_layout_graph_written_from_valid_pcb(tmp_path: Path):
|
||||
assert out.is_file()
|
||||
data = __import__("json").loads(out.read_text())
|
||||
assert "R1" in data["footprints"]
|
||||
|
||||
|
||||
def test_stackup_thickness_without_full_dielectrics(tmp_path: Path):
|
||||
p = tmp_path / "t.kicad_pcb"
|
||||
p.write_text("""(kicad_pcb (version 20240108)
|
||||
(net 0 "")
|
||||
(net 1 "VOUT")
|
||||
(setup
|
||||
(stackup
|
||||
(layer "F.Cu" (type "copper") (thickness 0.035mm))
|
||||
(layer "B.Cu" (type "copper") (thickness 0.035))
|
||||
)
|
||||
)
|
||||
(via (at 1 1) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 1))
|
||||
(arc (start 0 0) (end 2 0) (width 0.4) (layer "F.Cu") (net 1))
|
||||
)
|
||||
""")
|
||||
g = parse_kicad_pcb(p)
|
||||
assert g.stackup is not None
|
||||
assert g.stackup.copper_thickness_mm == pytest.approx(0.035)
|
||||
assert len(g.vias) == 1
|
||||
assert any(s.width == pytest.approx(0.4) and s.net == "VOUT" for s in g.segments)
|
||||
|
||||
@@ -394,12 +394,19 @@ def test_power_trace_ipc2221_errors_when_load_exceeds_ampacity():
|
||||
assert findings[0].recommendation
|
||||
|
||||
|
||||
def test_power_trace_uses_parsed_width_and_thickness():
|
||||
from backend.periscopex.pcb_power_thermal import check_pcb_power_traces
|
||||
|
||||
graph, cmap, layout = _ldo_graph_layout(i_load=0.05, width=1.0, thickness=0.035)
|
||||
findings = check_pcb_power_traces(graph, cmap, layout)
|
||||
assert findings == []
|
||||
|
||||
|
||||
def test_power_trace_skips_without_i_load():
|
||||
from backend.periscopex.pcb_power_thermal import check_pcb_power_traces
|
||||
|
||||
graph, cmap, layout = _ldo_graph_layout(i_load=10)
|
||||
graph.components["U1"].specs.values["i_load_a"] = None # type: ignore[union-attr]
|
||||
# drop i_load
|
||||
graph.components["U1"].specs = None
|
||||
assert check_pcb_power_traces(graph, cmap, layout) == []
|
||||
|
||||
@@ -502,6 +509,38 @@ def test_thermal_copper_warns_without_pour_or_vias():
|
||||
assert findings[0].recommendation
|
||||
|
||||
|
||||
def test_gnd_stitch_skips_tiny_gpio():
|
||||
from backend.periscopex.models import LayoutZone, PinConnection
|
||||
from backend.periscopex.pcb_power_thermal import check_pcb_gnd_stitch
|
||||
|
||||
graph = DesignGraph(
|
||||
components={
|
||||
"U1": Component(
|
||||
reference="U1", value="", footprint="",
|
||||
component_type=ComponentType.IC, mpn="X",
|
||||
pins={"1": "GPIO4"},
|
||||
),
|
||||
},
|
||||
nets={
|
||||
"GPIO4": Net(
|
||||
name="GPIO4", net_type=NetType.SIGNAL,
|
||||
pins=[PinConnection(component_ref="U1", pin_number="1")],
|
||||
),
|
||||
},
|
||||
)
|
||||
layout = LayoutGraph(
|
||||
footprints={},
|
||||
segments=[
|
||||
LayoutSegment(start=(0, 0), end=(0.1, 3), width=0.2, layer="F.Cu", net="GPIO4"),
|
||||
],
|
||||
zones=[
|
||||
LayoutZone(net="GND", layer="B.Cu", outlines=[[(0, -5), (20, -5), (20, 5), (0, 5)]]),
|
||||
],
|
||||
vias=[],
|
||||
)
|
||||
assert check_pcb_gnd_stitch(graph, layout) == []
|
||||
|
||||
|
||||
def test_gnd_stitch_info_when_signal_has_pour_but_no_via():
|
||||
from backend.periscopex.models import LayoutVia, LayoutZone, PinConnection
|
||||
from backend.periscopex.pcb_power_thermal import check_pcb_gnd_stitch
|
||||
@@ -511,12 +550,12 @@ def test_gnd_stitch_info_when_signal_has_pour_but_no_via():
|
||||
"U1": Component(
|
||||
reference="U1", value="", footprint="",
|
||||
component_type=ComponentType.IC, mpn="X",
|
||||
pins={"1": "SDA"},
|
||||
pins={"1": "USB_DP"},
|
||||
),
|
||||
},
|
||||
nets={
|
||||
"SDA": Net(
|
||||
name="SDA", net_type=NetType.SIGNAL,
|
||||
"USB_DP": Net(
|
||||
name="USB_DP", net_type=NetType.SIGNAL,
|
||||
pins=[PinConnection(component_ref="U1", pin_number="1")],
|
||||
),
|
||||
},
|
||||
@@ -524,17 +563,18 @@ def test_gnd_stitch_info_when_signal_has_pour_but_no_via():
|
||||
layout = LayoutGraph(
|
||||
footprints={},
|
||||
segments=[
|
||||
LayoutSegment(start=(0, 0), end=(20, 0), width=0.2, layer="F.Cu", net="SDA"),
|
||||
LayoutSegment(start=(0, 0), end=(20, 8), width=0.2, layer="F.Cu", net="USB_DP"),
|
||||
],
|
||||
zones=[
|
||||
LayoutZone(net="GND", layer="B.Cu", outlines=[[(0, -5), (20, -5), (20, 5), (0, 5)]]),
|
||||
LayoutZone(net="GND", layer="B.Cu", outlines=[[(0, -5), (20, -5), (20, 10), (0, 10)]]),
|
||||
],
|
||||
vias=[],
|
||||
)
|
||||
findings = check_pcb_gnd_stitch(graph, layout)
|
||||
assert findings and findings[0].rule_id == "PE-STCH-001"
|
||||
assert findings[0].status == "INFO"
|
||||
layout.vias = [LayoutVia(x=10, y=0, net="GND", drill=0.3)]
|
||||
assert findings[0].action
|
||||
layout.vias = [LayoutVia(x=10, y=4, net="GND", drill=0.3)]
|
||||
assert check_pcb_gnd_stitch(graph, layout) == []
|
||||
|
||||
|
||||
|
||||
@@ -262,6 +262,60 @@ def test_keepout_foreign_track_in_courtyard_is_ps_plc_004():
|
||||
assert len(plc) == 1
|
||||
assert plc[0].designator == "X1"
|
||||
assert plc[0].net == "GND"
|
||||
assert plc[0].finding_class == "REVIEW"
|
||||
assert plc[0].action
|
||||
|
||||
|
||||
def test_ic_courtyard_pad_nets_are_not_keepout_violations():
|
||||
"""GND/I2C into an IC courtyard is normal copper to that part's pads."""
|
||||
from backend.periscopex.models import Component, ComponentType, Net, NetType, PinConnection
|
||||
|
||||
cons = {
|
||||
"MCU": ComponentConstraints(
|
||||
mpn="MCU",
|
||||
pintable=[Pin(number="1", name="SDA")],
|
||||
absolute_maximum_ratings=[],
|
||||
rules=[],
|
||||
layout_rules=[{"kind": "keepout", "pin": "1"}],
|
||||
)
|
||||
}
|
||||
graph = DesignGraph(
|
||||
components={
|
||||
"U1": Component(
|
||||
reference="U1", value="", footprint="",
|
||||
component_type=ComponentType.IC, mpn="MCU",
|
||||
pins={"1": "SDA", "2": "GND"},
|
||||
),
|
||||
},
|
||||
nets={
|
||||
"SDA": Net(
|
||||
name="SDA", net_type=NetType.SIGNAL,
|
||||
pins=[PinConnection(component_ref="U1", pin_number="1")],
|
||||
),
|
||||
"GND": Net(
|
||||
name="GND", net_type=NetType.GROUND,
|
||||
pins=[PinConnection(component_ref="U1", pin_number="2")],
|
||||
),
|
||||
},
|
||||
)
|
||||
layout = LayoutGraph(
|
||||
footprints={
|
||||
"U1": LayoutFootprint(
|
||||
reference="U1", x=0, y=0, layer="F.Cu",
|
||||
pads=[
|
||||
LayoutPad(number="1", x=0.2, y=0.2, net="SDA"),
|
||||
LayoutPad(number="2", x=0.8, y=0.2, net="GND"),
|
||||
],
|
||||
courtyard=[(0.0, 0.0), (1.0, 0.0), (1.0, 1.0), (0.0, 1.0)],
|
||||
),
|
||||
},
|
||||
segments=[
|
||||
LayoutSegment(start=(0.4, 0.4), end=(0.6, 0.4), width=0.2, layer="F.Cu", net="GND"),
|
||||
LayoutSegment(start=(0.3, 0.5), end=(0.5, 0.5), width=0.2, layer="F.Cu", net="SDA"),
|
||||
],
|
||||
)
|
||||
findings = check_placement(graph, cons, layout)
|
||||
assert [f for f in findings if f.rule_id == "PE-PLC-004"] == []
|
||||
|
||||
|
||||
def test_keepout_own_net_in_courtyard_is_silent():
|
||||
|
||||
Reference in New Issue
Block a user