Prefer .kicad_pcb pad nets when building the design graph.
Schematic geometry on KiCad 10 boards was swapping rails and inventing floating pins; board connectivity is authoritative when a PCB is uploaded. Co-authored-by: Cursor <cursoragent@cursor.com>
This commit is contained in:
Cursor
@@ -254,6 +254,7 @@ def build_graph(
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mpn_col: str = "Manufacturer Part Number",
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skipped: list[SkippedItem] | None = None,
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include_subdesigns: set[str] | None = None,
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pcb_path: str | Path | None = None,
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) -> DesignGraph:
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"""Build a DesignGraph deterministically from project files.
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@@ -264,6 +265,9 @@ def build_graph(
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4. Resolve passive specs from patterns + cached component models
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5. Assemble components with classified type, linked constraints, and specs
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6. Assemble nets with inferred type/voltage and enriched pin names
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When ``pcb_path`` points at a ``.kicad_pcb``, pad nets from the board replace
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schematic-derived connectivity (KiCad board nets are authoritative).
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"""
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# Parse BOM first so we can feed known refs into the netlist parser —
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# PADS-PCB netlists allow multi-word designators (e.g. "CV GND"), which
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@@ -284,6 +288,17 @@ def build_graph(
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known_refs=set(bom.keys()),
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include_subdesigns=include_subdesigns,
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)
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if pcb_path is not None:
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pcb = Path(pcb_path)
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if pcb.is_file():
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from backend.pinscopex.parsers_kicad_pcb import nets_from_pcb, parse_kicad_pcb
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layout = parse_kicad_pcb(pcb)
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pcb_nets = nets_from_pcb(layout)
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if pcb_nets:
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raw_nets = pcb_nets
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for ref, fp in layout.footprints.items():
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parts.setdefault(ref, fp.footprint or "")
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if fmt.startswith("kicad"):
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from backend.pinscopex.parsers_kicad import kicad_part_fields
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for ref, extra in kicad_part_fields(netlist_path).items():
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@@ -45,16 +45,62 @@ def _prop(node: object, key: str) -> str:
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def _pad_net(pad: object) -> str:
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n = _kid(pad, "net")
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if n and len(n) >= 3:
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if not n or len(n) < 2:
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return ""
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# KiCad 9/10 often stores ``(net "GND")`` without a numeric code.
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if len(n) == 2 and not isinstance(n[1], list):
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return str(n[1])
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# Legacy ``(net 3 "GND")``.
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if len(n) >= 3:
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return str(n[2])
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return ""
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def _normalize_pcb_net_name(name: str) -> str:
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"""Strip KiCad root-sheet ``/`` prefixes; keep empty / unconnected as-is."""
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n = (name or "").strip()
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if not n:
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return ""
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while n.startswith("/"):
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n = n[1:]
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return n
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def nets_from_pcb(layout: LayoutGraph) -> dict[str, list[tuple[str, str]]]:
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"""Pad connectivity from a parsed board — authoritative when sch geometry fails."""
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nets: dict[str, list[tuple[str, str]]] = {}
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seen: set[tuple[str, str, str]] = set()
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for ref, fp in layout.footprints.items():
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for pad in fp.pads:
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raw = pad.net or ""
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if not raw:
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continue
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name = _normalize_pcb_net_name(raw)
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if not name:
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continue
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key = (name, ref, pad.number)
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if key in seen:
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continue
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seen.add(key)
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nets.setdefault(name, []).append((ref, pad.number))
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return nets
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def _net_name(node: object, nets: dict[str, int]) -> str:
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n = _kid(node, "net")
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if not n or len(n) < 2:
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named = _val(node, "net_name")
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return named
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# ``(net "GND")`` or ``(net 1)`` or ``(net 1 "GND")``
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if len(n) == 2 and not isinstance(n[1], list):
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token = n[1]
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if isinstance(token, str) and not str(token).replace(".", "", 1).isdigit():
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return str(token)
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try:
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code = int(_fnum(token))
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except (TypeError, ValueError):
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return str(token)
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return next((name for name, c in nets.items() if c == code), str(code))
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if len(n) >= 3:
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return str(n[2])
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try:
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@@ -1565,6 +1565,7 @@ async def _stage_graph_build(ctx: PipelineContext) -> None:
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if ctx.meta.netlist_subdesigns is not None
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else None
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),
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pcb_path=ctx.ws.local_path("uploads/pcb.kicad_pcb"),
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)
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graph_path = ctx.ws.local_path("design_graph.json")
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@@ -2130,6 +2131,7 @@ async def run_regen_pipeline(
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if meta.netlist_subdesigns is not None
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else None
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),
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pcb_path=ws.local_path("uploads/pcb.kicad_pcb"),
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)
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graph_path = ws.local_path("design_graph.json")
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@@ -2,6 +2,14 @@
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What's new in Pinscope.
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## 2.26.5 — 2026-09-11 — Prefer PCB nets for connectivity
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When a `.kicad_pcb` is present, pad nets from the board drive the design graph. Schematic geometry alone was inventing swapped rails (GND↔3V3) and floating pins on good KiCad 10 designs.
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- [Fixed] KiCad 10 `(net "Name")` pad form.
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- [Fixed] Graph build overrides sch nets with board connectivity; `/NET` → `NET`.
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- [Test] PCB nets beat a misleading schematic.
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## 2.26.4 — 2026-09-11 — KiCad power nets merge
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`.kicad_sch` connectivity treated every `GND` power flag as its own island (`GND_`, `GND__`…), so the reviewer invented swapped rails and floating pins on good designs.
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@@ -84,6 +84,84 @@ def test_empty_board_parses(tmp_path: Path):
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assert g.segments == []
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_PCB_V10 = """(kicad_pcb (version 20260206) (generator pcbnew)
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(footprint "Package_TO_SOT_SMD:SOT-23-5"
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(layer "F.Cu")
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(at 0 0 0)
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(property "Reference" "U3" (at 0 0 0) (effects (font (size 1 1))))
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(pad "1" smd rect (at 0 0) (size 1 1) (layers "F.Cu") (net "VSYS"))
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(pad "2" smd rect (at 1 0) (size 1 1) (layers "F.Cu") (net "GND"))
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(pad "5" smd rect (at 2 0) (size 1 1) (layers "F.Cu") (net "3V3_DIGITAL"))
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)
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(footprint "RF_Module:ESP"
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(layer "F.Cu")
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(at 10 0 0)
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(property "Reference" "U5" (at 0 0 0) (effects (font (size 1 1))))
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(pad "1" smd rect (at 0 0) (size 1 1) (layers "F.Cu") (net "GND"))
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(pad "2" smd rect (at 1 0) (size 1 1) (layers "F.Cu") (net "3V3_DIGITAL"))
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(pad "3" smd rect (at 2 0) (size 1 1) (layers "F.Cu") (net "/ESP32_EN"))
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)
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)
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"""
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def test_kicad10_pad_net_string_form(tmp_path: Path):
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from backend.pinscopex.parsers_kicad_pcb import nets_from_pcb
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p = tmp_path / "v10.kicad_pcb"
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p.write_text(_PCB_V10)
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g = parse_kicad_pcb(p)
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assert g.footprints["U3"].pads[1].net == "GND"
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nets = nets_from_pcb(g)
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assert ("U3", "2") in nets["GND"]
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assert ("U3", "5") in nets["3V3_DIGITAL"]
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assert ("U5", "3") in nets["ESP32_EN"] # leading / stripped
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def test_build_graph_prefers_pcb_nets_over_sch(tmp_path: Path):
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"""Board pad nets win when sch geometry would swap rails."""
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from backend.pinscopex.graph import build_graph
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sch = tmp_path / "netlist.kicad_sch"
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# Minimal sch: only needs to parse as kicad_sch with some parts.
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sch.write_text("""(kicad_sch (version 20250114) (uuid "1")
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(lib_symbols
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(symbol "Device:R"
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(pin passive (at 0 3.81 90) (length 2.54)
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(name "~" (effects (font (size 1.27 1.27))))
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(number "1" (effects (font (size 1.27 1.27))))
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)
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(pin passive (at 0 -3.81 90) (length 2.54)
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(name "~" (effects (font (size 1.27 1.27))))
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(number "2" (effects (font (size 1.27 1.27))))
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)
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)
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)
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(symbol (lib_id "Device:R") (at 0 0 0) (unit 1) (uuid "a")
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(property "Reference" "R1" (at 0 0 0) (effects (font (size 1.27 1.27))))
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(property "Value" "10k" (at 0 0 0) (effects (font (size 1.27 1.27))))
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(pin "1" (uuid "p1")) (pin "2" (uuid "p2"))
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)
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(global_label "GND" (at 0 3.81 0) (uuid "b"))
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)
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""")
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pcb = tmp_path / "pcb.kicad_pcb"
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pcb.write_text(_PCB_V10)
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bom = tmp_path / "bom.csv"
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bom.write_text(
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"Reference,Value,Footprint,Manufacturer Part Number\n"
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"U3,AP2112,SOT23,\nU5,ESP32,,\nR1,10k,,\n"
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)
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g = build_graph(
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sch, bom, tmp_path / "ex", tmp_path / "pat", tmp_path / "mod",
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pcb_path=pcb,
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)
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assert g.components["U3"].pins["2"] == "GND"
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assert g.components["U3"].pins["5"] == "3V3_DIGITAL"
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assert g.components["U5"].pins["1"] == "GND"
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assert g.components["U5"].pins["2"] == "3V3_DIGITAL"
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def test_upload_pcb_sets_has_pcb(tmp_path: Path):
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from fastapi.testclient import TestClient
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from backend.main import app
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