Open a KiCad project folder: schematic + PCB, no netlist.

Apri progetto KiCad picks the folder that contains .kicad_pro and loads
sibling hierarchical sheets and the matching .kicad_pcb. Connectivity and
MPN/PNM/Value come from the schematic; a leftover PADS .asc is ignored.
A lone .kicad_pro upload is rejected unless that path exists on disk.

tests/test_netlist_bundle.py

@@ -256,7 +256,7 @@ def test_zip_pipeline_workspace_reparses_hierarchy(tmp_path: Path):
 
 
 def test_kicad_pcb_bytes_are_not_parsed_as_pads(tmp_path: Path):
-    with pytest.raises(ValueError, match="board"):
+    with pytest.raises(ValueError, match="circuito stampato|board"):
         materialize_netlist_upload(
             [("board.kicad_pcb", b"(kicad_pcb (version 1)\n")],
             tmp_path / "work",