Add schematic filter topology and LDO/resistor thermal checks.
Match RC/LC/π/T without inventing fc, compare to ADC rate only when specs list it, and skip ferrite DCR unless the IC gives a limit. LDO Tj uses I_load not Iout_max, and missing θJA stays INFO. Co-authored-by: Cursor <cursoragent@cursor.com>
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Cursor
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"""Filter topology matcher — RC/LC/π/T fc, ADC compare only with specs."""
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from __future__ import annotations
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from backend.pinscopex.filter_check import check_filters
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from backend.pinscopex.models import (
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CapacitorSpecs,
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Component,
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ComponentConstraints,
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ComponentType,
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DesignGraph,
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InductorSpecs,
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Net,
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NetType,
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Pin,
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PinConnection,
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ResistorSpecs,
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SimpleComponentSpecs,
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)
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def _graph(components, nets):
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net_objs = {
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name: Net(
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name=name, net_type=ntype,
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pins=[PinConnection(component_ref=r, pin_number=str(p)) for r, p in conns],
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)
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for name, (ntype, conns) in nets.items()
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}
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return DesignGraph(components=components, nets=net_objs)
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def _res(ref, ohms, n1, n2):
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return Component(
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reference=ref, value=str(ohms), footprint="",
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component_type=ComponentType.RESISTOR, mpn=ref,
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pins={"1": n1, "2": n2},
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specs=ResistorSpecs(value_ohms=ohms, value_formatted=str(ohms)),
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)
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def _cap(ref, farads, net):
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return Component(
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reference=ref, value="", footprint="",
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component_type=ComponentType.CAPACITOR, mpn=ref,
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pins={"1": net, "2": "GND"},
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specs=CapacitorSpecs(value_farads=farads, value_formatted="x"),
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)
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def _l(ref, henries, n1, n2, ferrite=False, dcr=None):
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sub = "passive.ferrite_bead" if ferrite else "passive.inductor"
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kwargs = dict(value_formatted="x", component_subtype=sub, dcr_ohms=dcr)
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if ferrite:
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specs = InductorSpecs(impedance_ohm=100.0, value_henries=henries, **kwargs)
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else:
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specs = InductorSpecs(value_henries=henries, **kwargs)
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return Component(
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reference=ref, value="", footprint="",
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component_type=ComponentType.INDUCTOR, mpn=ref,
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component_subtype=sub,
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pins={"1": n1, "2": n2}, specs=specs,
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)
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def _ic(ref="U1", pins=None, values=None, mpn="UTEST"):
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return Component(
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reference=ref, value="", footprint="",
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component_type=ComponentType.IC, mpn=mpn,
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pins=pins or {"1": "AIN", "2": "GND"},
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specs=SimpleComponentSpecs(
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specs_type="ic", values=values or {},
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) if values is not None else None,
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)
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def test_rc_reports_fc_info_without_adc_rate():
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# 1k * 100nF -> fc ≈ 1.59 kHz; no sample rate → INFO not WARNING.
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g = _graph(
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{
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"U1": _ic(),
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"R1": _res("R1", 1e3, "AIN", "FILT"),
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"C1": _cap("C1", 100e-9, "FILT"),
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},
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{
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"AIN": (NetType.SIGNAL, [("U1", "1"), ("R1", "1")]),
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"FILT": (NetType.SIGNAL, [("R1", "2"), ("C1", "1")]),
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"GND": (NetType.GROUND, [("U1", "2"), ("C1", "2")]),
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},
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)
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findings = check_filters(g)
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assert len(findings) == 1
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assert findings[0].rule_id == "PS-FLT-001"
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assert findings[0].status == "INFO"
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assert findings[0].source == "filter_check"
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def test_rc_vs_adc_rate_is_warning():
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g = _graph(
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{
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"U1": _ic(values={"adc_sample_rate": 1e6}),
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"R1": _res("R1", 1e3, "AIN", "FILT"),
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"C1": _cap("C1", 100e-9, "FILT"),
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},
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{
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"AIN": (NetType.SIGNAL, [("U1", "1"), ("R1", "1")]),
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"FILT": (NetType.SIGNAL, [("R1", "2"), ("C1", "1")]),
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"GND": (NetType.GROUND, [("U1", "2"), ("C1", "2")]),
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},
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)
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findings = check_filters(g)
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assert len(findings) == 1
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assert findings[0].rule_id == "PS-FLT-002"
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assert findings[0].status == "WARNING"
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def test_pullup_plus_decoupling_is_not_a_filter():
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g = _graph(
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{
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"U1": Component(
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reference="U1", value="", footprint="",
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component_type=ComponentType.IC, mpn="UTEST",
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pins={"1": "SDA", "2": "3V3", "3": "GND"},
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),
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"R1": _res("R1", 4700, "SDA", "3V3"),
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"C1": _cap("C1", 100e-9, "3V3"),
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},
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{
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"SDA": (NetType.SIGNAL, [("U1", "1"), ("R1", "1")]),
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"3V3": (NetType.POWER, [("U1", "2"), ("R1", "2"), ("C1", "1")]),
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"GND": (NetType.GROUND, [("U1", "3"), ("C1", "2")]),
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},
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)
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assert check_filters(g) == []
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def test_missing_c_value_does_not_invent_fc_warning():
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c = Component(
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reference="C1", value="", footprint="",
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component_type=ComponentType.CAPACITOR, mpn="C1",
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pins={"1": "FILT", "2": "GND"},
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)
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g = _graph(
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{
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"U1": _ic(values={"adc_sample_rate": 1e6}),
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"R1": _res("R1", 1e3, "AIN", "FILT"),
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"C1": c,
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},
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{
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"AIN": (NetType.SIGNAL, [("U1", "1"), ("R1", "1")]),
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"FILT": (NetType.SIGNAL, [("R1", "2"), ("C1", "1")]),
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"GND": (NetType.GROUND, [("U1", "2"), ("C1", "2")]),
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},
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)
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findings = check_filters(g)
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assert len(findings) == 1
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assert findings[0].rule_id == "PS-FLT-001"
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assert findings[0].status == "INFO"
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def test_pi_and_t_need_l_and_c():
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g_pi = _graph(
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{
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"L1": _l("L1", 10e-6, "A", "B"),
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"C1": _cap("C1", 100e-9, "A"),
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"C2": _cap("C2", 100e-9, "B"),
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},
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{
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"A": (NetType.SIGNAL, [("L1", "1"), ("C1", "1")]),
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"B": (NetType.SIGNAL, [("L1", "2"), ("C2", "1")]),
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"GND": (NetType.GROUND, [("C1", "2"), ("C2", "2")]),
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},
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)
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pi = check_filters(g_pi)
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assert len(pi) == 1 and pi[0].rule_id == "PS-FLT-001" and "π" in pi[0].finding
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g_t = _graph(
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{
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"L1": _l("L1", 10e-6, "A", "MID"),
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"L2": _l("L2", 10e-6, "MID", "B"),
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"C1": _cap("C1", 100e-9, "MID"),
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},
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{
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"A": (NetType.SIGNAL, [("L1", "1")]),
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"MID": (NetType.SIGNAL, [("L1", "2"), ("L2", "1"), ("C1", "1")]),
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"B": (NetType.SIGNAL, [("L2", "2")]),
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"GND": (NetType.GROUND, [("C1", "2")]),
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},
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)
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t = check_filters(g_t)
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assert len(t) == 1 and "T" in t[0].finding
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def test_ferrite_dcr_warns_only_with_datasheet_limit():
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cons = {
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"UTEST": ComponentConstraints(
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mpn="UTEST",
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pintable=[Pin(number=1, name="VDDA"), Pin(number=2, name="GND")],
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absolute_maximum_ratings=[], rules=[],
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)
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}
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fb = _l("FB1", None, "VDDA", "3V3", ferrite=True, dcr=2.0)
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g = _graph(
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{
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"U1": _ic(pins={"1": "VDDA", "2": "GND"}, values={}),
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"FB1": fb,
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"C1": _cap("C1", 100e-9, "VDDA"),
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},
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{
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"VDDA": (NetType.POWER, [("U1", "1"), ("FB1", "1"), ("C1", "1")]),
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"3V3": (NetType.POWER, [("FB1", "2")]),
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"GND": (NetType.GROUND, [("U1", "2"), ("C1", "2")]),
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},
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)
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assert not any(f.rule_id == "PS-FLT-003" for f in check_filters(g, cons))
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g2 = _graph(
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{
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"U1": _ic(pins={"1": "VDDA", "2": "GND"}, values={"max_ferrite_dcr_ohms": 0.5}),
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"FB1": fb,
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"C1": _cap("C1", 100e-9, "VDDA"),
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},
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{
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"VDDA": (NetType.POWER, [("U1", "1"), ("FB1", "1"), ("C1", "1")]),
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"3V3": (NetType.POWER, [("FB1", "2")]),
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"GND": (NetType.GROUND, [("U1", "2"), ("C1", "2")]),
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},
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)
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dcr = [f for f in check_filters(g2, cons) if f.rule_id == "PS-FLT-003"]
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assert len(dcr) == 1 and dcr[0].status == "WARNING"
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@@ -0,0 +1,144 @@
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"""LDO/resistor thermal — no invented I_load or θJA."""
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from __future__ import annotations
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from backend.pinscopex.models import (
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Component,
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ComponentConstraints,
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ComponentType,
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DesignGraph,
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Net,
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NetType,
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Pin,
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PinConnection,
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ResistorSpecs,
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SimpleComponentSpecs,
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)
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from backend.pinscopex.thermal_check import check_thermal
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def _graph(components, nets):
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net_objs = {}
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for name, (ntype, volt, conns) in nets.items():
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net_objs[name] = Net(
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name=name, net_type=ntype, voltage=volt,
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pins=[PinConnection(component_ref=r, pin_number=str(p)) for r, p in conns],
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)
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return DesignGraph(components=components, nets=net_objs)
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def _ldo(values, subtype="ic.power.ldo"):
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return Component(
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reference="U1", value="", footprint="",
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component_type=ComponentType.IC, component_subtype=subtype,
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mpn="LDOX",
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pins={"1": "VIN", "2": "VOUT", "3": "GND"},
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specs=SimpleComponentSpecs(specs_type="ic", component_subtype=subtype, values=values),
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)
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def _cons():
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return {
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"LDOX": ComponentConstraints(
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mpn="LDOX",
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component_subtype="ic.power.ldo",
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pintable=[
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Pin(number=1, name="VIN"),
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Pin(number=2, name="VOUT"),
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Pin(number=3, name="GND"),
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],
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absolute_maximum_ratings=[], rules=[],
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)
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}
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def test_ldo_without_theta_ja_is_info():
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g = _graph(
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{"U1": _ldo({"i_load_a": 0.2})},
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{
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"VIN": (NetType.POWER, 5.0, [("U1", "1")]),
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"VOUT": (NetType.POWER, 3.3, [("U1", "2")]),
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"GND": (NetType.GROUND, 0.0, [("U1", "3")]),
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},
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)
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findings = check_thermal(g, _cons())
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assert len(findings) == 1
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assert findings[0].rule_id == "PS-TH-001"
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assert findings[0].status == "INFO"
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assert "theta_ja" in findings[0].finding.lower() or "theta_ja" in findings[0].why.lower()
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def test_iout_max_is_not_used_as_load():
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g = _graph(
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{"U1": _ldo({"iout_max_a": 0.5, "theta_ja": 160})},
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{
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"VIN": (NetType.POWER, 5.0, [("U1", "1")]),
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"VOUT": (NetType.POWER, 3.3, [("U1", "2")]),
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"GND": (NetType.GROUND, 0.0, [("U1", "3")]),
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},
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)
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assert check_thermal(g, _cons()) == []
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def test_ldo_hot_tj_is_warning():
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# 0.5 A * 1.7 V = 0.85 W * 160 °C/W + 25 = 161 °C
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g = _graph(
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{"U1": _ldo({"i_load_a": 0.5, "theta_ja": 160})},
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{
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"VIN": (NetType.POWER, 5.0, [("U1", "1")]),
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"VOUT": (NetType.POWER, 3.3, [("U1", "2")]),
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"GND": (NetType.GROUND, 0.0, [("U1", "3")]),
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},
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)
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findings = check_thermal(g, _cons())
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assert len(findings) == 1
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assert findings[0].rule_id == "PS-TH-002"
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assert findings[0].status == "WARNING"
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def test_shunt_over_rating_is_warning():
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r = Component(
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reference="R1", value="1", footprint="",
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component_type=ComponentType.RESISTOR, mpn="R1",
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pins={"1": "A", "2": "B"},
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specs=ResistorSpecs(value_ohms=1.0, value_formatted="1", power_rating_w="0.125"),
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)
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g = _graph(
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{"R1": r},
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{
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"A": (NetType.POWER, 3.3, [("R1", "1")]),
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"B": (NetType.POWER, 0.0, [("R1", "2")]),
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},
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)
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findings = check_thermal(g)
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assert len(findings) == 1
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assert findings[0].rule_id == "PS-TH-003"
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assert findings[0].status == "WARNING"
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def test_led_resistor_within_rating_is_silent():
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led = Component(
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reference="D1", value="LED", footprint="",
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component_type=ComponentType.DISCRETE, component_subtype="discrete.led",
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mpn="LEDX",
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pins={"A": "+5V", "K": "NetK"},
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specs=SimpleComponentSpecs(
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specs_type="discrete", component_subtype="discrete.led",
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values={"forward_voltage_v": 2.0, "forward_current_a": "20mA"},
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),
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)
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r = Component(
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reference="R1", value="330", footprint="",
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component_type=ComponentType.RESISTOR, mpn="R1",
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pins={"1": "NetK", "2": "GND"},
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specs=ResistorSpecs(value_ohms=330.0, value_formatted="330", power_rating_w="0.125"),
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)
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g = _graph(
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{"D1": led, "R1": r},
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{
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"+5V": (NetType.POWER, 5.0, [("D1", "A")]),
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"NetK": (NetType.SIGNAL, None, [("D1", "K"), ("R1", "1")]),
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"GND": (NetType.GROUND, 0.0, [("R1", "2")]),
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},
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)
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assert check_thermal(g) == []
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