Rebrand Pinscope to Periscope across product and codebase.
Rename the core package to periscopex, update UI/docs/Docker/deploy defaults to periscope.michelebigi.it, and keep legacy version/storage key aliases so existing projects keep working. Co-authored-by: Cursor <cursoragent@cursor.com>
This commit is contained in:
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"""Deterministic supply decoupling and I2C/reset pull-up checks.
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These only fire when the graph already shows a pintable supply pin, an I2C
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net/pin name, or a reset pin — they do not guess capacitor values, mux
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alt-functions, or datasheet µF minima.
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"""
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from __future__ import annotations
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import re
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from backend.periscopex.models import (
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CapacitorSpecs,
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Component,
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ComponentConstraints,
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ComponentType,
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DesignGraph,
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Finding,
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NetType,
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ResistorSpecs,
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)
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from backend.periscopex.validate import _match_constraints
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from backend.periscopex.led_current_check import _parse_resistance
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from backend.periscopex.resolve_passives import _parse_spice_value
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_SUPPLY_PIN_RE = re.compile(
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r"(?:^|[_/])(VDD|VCC|VDDA|VDDD|VDDIO|DVDD|AVDD|IOVDD|VDD33|VDD18|"
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r"VIN|VBAT|VBUS|VCORE)(?:$|[_/\d])",
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re.IGNORECASE,
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)
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_RAIL_PIN_RE = re.compile(r"^(?:\+?\d+V\d*)$", re.IGNORECASE)
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_NOT_SUPPLY_RE = re.compile(
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r"\b(VSS|GND|VEE|VOUT|VREF|SW|LX|FB|BOOT|NC|VPP)\b",
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re.IGNORECASE,
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)
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_I2C_RE = re.compile(r"(?:^|[^A-Za-z0-9])(SDA|SCL)(\d+)?(?:$|[^A-Za-z0-9])", re.IGNORECASE)
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_SPI_NAME_RE = re.compile(r"(?i)\b(MISO|MOSI|SCLK|SCK)\b")
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_RESET_RE = re.compile(
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r"\b(N?RST(?:N|B)?|NRST|RESET(?:_?N|_?B)?|NRESET|CHIP_PU)\b",
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re.IGNORECASE,
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)
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_NC_NET_RE = re.compile(
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r"^(?:n/?c|n\.c\.|nc|unconnected|no[_-]?connect|not[_-]?connected)$",
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re.IGNORECASE,
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)
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_OUT_PIN_RE = re.compile(
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r"(?:^|[_/])(VOUT|V_OUT|VO|VREG|SWOUT)(?:$|[_/\d])",
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re.IGNORECASE,
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)
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_ACTIVE_LOW_RESET_RE = re.compile(
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r"(?:N/?RST|NRST|NRESET|RESET[_-]?N|RSTN)\b",
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re.IGNORECASE,
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)
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# NXP UM10204-style Rp window, widened so 2.2k–10k never false-positives.
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_RP_MIN_OHM = 1_000.0
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_RP_MAX_OHM = 22_000.0
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_VDD_MIN_FARADS = 50e-9
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_VOUT_MIN_FARADS = 0.47e-6
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def check_supply_decoupling(
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graph: DesignGraph,
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constraints_map: dict[str, ComponentConstraints],
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) -> list[Finding]:
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"""WARNING when an IC supply/VOUT net has no capacitor to ground, or
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only farads well below a typical Cin/Cout when every cap is valued."""
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findings: list[Finding] = []
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seen_nets: set[str] = set()
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for ref, comp in sorted(graph.components.items()):
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if comp.component_type != ComponentType.IC:
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continue
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cons = _match_constraints(comp.mpn or comp.value, constraints_map)
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for pin_num, net_name in sorted(comp.pins.items(), key=lambda x: str(x[0])):
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if net_name in seen_nets:
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continue
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if _is_nc_net(net_name):
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continue
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role = None
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if _is_ic_supply_pin(graph, cons, pin_num, net_name):
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role = "supply"
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elif _is_regulator_output_pin(cons, pin_num):
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role = "output"
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if role is None:
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continue
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seen_nets.add(net_name)
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pin_label = _pin_label(cons, pin_num, net_name)
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if not _capacitor_to_ground(graph, net_name):
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findings.append(Finding(
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designator=ref,
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mpn=comp.mpn or "",
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aspect="decoupling",
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source="supply_decoupling_check",
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source_page=None,
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status="WARNING",
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finding=(
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f"{ref} supply net '{net_name}' ({pin_label}) has no "
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f"capacitor to ground."
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if role == "supply"
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else (
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f"{ref} regulator output '{net_name}' ({pin_label}) "
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f"has no Cout capacitor to ground."
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)
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),
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why=(
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f"Pin {pin_label} sits on '{net_name}' and that net has no "
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f"capacitor whose other end is ground. Local decoupling "
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f"may be missing (or only present on a different island "
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f"behind a ferrite)."
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),
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recommendation=(
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f"Add a decoupling capacitor from '{net_name}' to ground "
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f"near {ref}."
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),
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reference="netlist topology",
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net=net_name,
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pins=[f"{ref}.{pin_num}"],
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rule_id="PE-DEC-001",
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))
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continue
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min_f = _VOUT_MIN_FARADS if role == "output" else _VDD_MIN_FARADS
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max_c = _max_known_cap_farads(graph, net_name)
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if max_c is not None and max_c < min_f:
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findings.append(Finding(
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designator=ref,
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mpn=comp.mpn or "",
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aspect="decoupling",
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source="supply_decoupling_check",
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source_page=None,
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status="WARNING",
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finding=(
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f"{ref} net '{net_name}' ({pin_label}) only has "
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f"{max_c * 1e6:.3g} µF to ground; typical "
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f"{'Cout' if role == 'output' else 'decoupling'} is larger."
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),
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why=(
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"Cap values are known on this net and the largest is "
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"below a wide typical minimum. This is not a datasheet "
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"µF requirement — treat as a sizing hint."
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),
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recommendation=(
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f"Add bulk capacitance on '{net_name}' (often ≥1 µF on "
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f"LDO VOUT, ≥100 nF on MCU VDD) if the datasheet agrees."
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),
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reference="netlist topology",
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net=net_name,
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pins=[f"{ref}.{pin_num}"],
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rule_id="PE-DEC-002",
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))
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return findings
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def check_i2c_pullups(
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graph: DesignGraph,
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constraints_map: dict[str, ComponentConstraints],
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) -> list[Finding]:
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"""WARNING when an SDA/SCL net has no resistor to a power rail."""
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findings: list[Finding] = []
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seen_nets: set[str] = set()
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for ref, comp in sorted(graph.components.items()):
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if comp.component_type != ComponentType.IC:
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continue
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cons = _match_constraints(comp.mpn or comp.value, constraints_map)
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for pin_num, net_name in sorted(comp.pins.items(), key=lambda x: str(x[0])):
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if net_name in seen_nets:
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continue
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if _is_nc_net(net_name):
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continue
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if not _is_i2c_pin(graph, cons, pin_num, net_name):
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continue
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seen_nets.add(net_name)
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net = graph.nets.get(net_name)
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if net and net.net_type in (NetType.POWER, NetType.GROUND):
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continue
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if _resistor_to_power(graph, net_name):
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ohms = _parallel_pullup_ohms(graph, net_name)
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if ohms is not None and (
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ohms < _RP_MIN_OHM or ohms > _RP_MAX_OHM
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):
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pin_label = _pin_label(cons, pin_num, net_name)
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findings.append(Finding(
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designator=ref,
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mpn=comp.mpn or "",
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aspect="i2c_pullup",
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source="i2c_pullup_check",
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source_page=None,
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status="WARNING",
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finding=(
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f"I2C net '{net_name}' ({ref} {pin_label}) pull-up "
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f"is {ohms:.3g} Ω (wide NXP-style band "
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f"{_RP_MIN_OHM:.0f}–{_RP_MAX_OHM:.0f} Ω)."
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),
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why=(
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"UM10204 Rp depends on Vdd, Iol and bus capacitance. "
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"This bound is wide on purpose; 2.2–10 kΩ at 3.3 V "
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"is typical. Unknown resistor values are not sized."
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),
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recommendation=(
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f"Use a pull-up on '{net_name}' inside "
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f"{_RP_MIN_OHM:.0f}–{_RP_MAX_OHM:.0f} Ω unless the "
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f"bus capacitance/Iol calculation says otherwise."
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),
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reference="NXP UM10204 (wide bound)",
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net=net_name,
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pins=[f"{ref}.{pin_num}"],
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rule_id="PE-I2C-002",
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))
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continue
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pin_label = _pin_label(cons, pin_num, net_name)
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findings.append(Finding(
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designator=ref,
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mpn=comp.mpn or "",
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aspect="i2c_pullup",
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source="i2c_pullup_check",
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source_page=None,
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status="WARNING",
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finding=(
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f"I2C net '{net_name}' ({ref} {pin_label}) has no pull-up "
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f"resistor to a power rail."
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),
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why=(
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f"SDA/SCL is open-drain. Without a resistor from "
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f"'{net_name}' to a supply, the bus cannot idle high."
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),
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recommendation=(
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f"Add a pull-up (typically 2.2–10 kΩ) from '{net_name}' "
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f"to the I2C I/O rail."
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),
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reference="netlist topology",
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net=net_name,
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pins=[f"{ref}.{pin_num}"],
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rule_id="PE-I2C-001",
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))
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return findings
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def check_reset_pullups(
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graph: DesignGraph,
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constraints_map: dict[str, ComponentConstraints],
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) -> list[Finding]:
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"""WARNING when a reset pin's net is only this IC and has no pull-up."""
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findings: list[Finding] = []
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seen_nets: set[str] = set()
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for ref, comp in sorted(graph.components.items()):
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if comp.component_type != ComponentType.IC:
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continue
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cons = _match_constraints(comp.mpn or comp.value, constraints_map)
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for pin_num, net_name in sorted(comp.pins.items(), key=lambda x: str(x[0])):
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if net_name in seen_nets:
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continue
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if _is_nc_net(net_name):
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continue
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if not _is_reset_pin(graph, cons, pin_num, net_name):
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continue
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seen_nets.add(net_name)
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net = graph.nets.get(net_name)
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if net and net.net_type in (NetType.POWER, NetType.GROUND):
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continue
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if _other_ic_on_net(graph, net_name, ref):
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continue
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pin_label = _pin_label(cons, pin_num, net_name)
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if _is_active_low_reset(cons, pin_num, net_name) and _resistor_to_ground(
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graph, net_name
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):
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findings.append(Finding(
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designator=ref,
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mpn=comp.mpn or "",
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aspect="reset_pullup",
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source="reset_pullup_check",
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source_page=None,
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status="WARNING",
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finding=(
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f"{ref} active-low reset '{net_name}' ({pin_label}) "
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f"has a pull-down to ground."
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),
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why=(
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"An active-low NRST/RESET_N pin held down by a resistor "
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"will sit in reset unless a stronger pull-up wins. "
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"Datasheets that omit an internal pull-up expect a pull-up, "
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"not a pull-down."
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),
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recommendation=(
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f"Remove the pull-down on '{net_name}' or replace it "
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f"with a pull-up to the I/O rail."
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),
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reference="netlist topology",
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net=net_name,
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pins=[f"{ref}.{pin_num}"],
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rule_id="PE-RST-002",
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))
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if _resistor_to_power(graph, net_name):
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continue
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findings.append(Finding(
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designator=ref,
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mpn=comp.mpn or "",
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aspect="reset_pullup",
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source="reset_pullup_check",
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source_page=None,
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status="WARNING",
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finding=(
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f"{ref} reset pin {pin_label} on '{net_name}' has no "
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f"pull-up and no other IC driving the net."
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),
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why=(
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f"The net only lands on {ref} (plus passives). Without a "
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f"resistor to a supply, an active-low reset input can float."
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),
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recommendation=(
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f"Add a pull-up to the I/O rail, or drive '{net_name}' "
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f"from a reset supervisor / GPIO."
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),
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reference="netlist topology",
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net=net_name,
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pins=[f"{ref}.{pin_num}"],
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rule_id="PE-RST-001",
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))
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return findings
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def _pin_label(cons: ComponentConstraints | None, pin_num: str, net_name: str) -> str:
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if cons:
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pin = cons.pin_by_number(pin_num)
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if pin and pin.name:
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return f"{pin_num} ({pin.name})"
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return str(pin_num)
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def _is_nc_net(name: str) -> bool:
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return bool(_NC_NET_RE.match((name or "").strip()))
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def _pin_name_tokens(cons: ComponentConstraints | None, pin_num: str) -> list[str]:
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"""Slash-separated pin *name* tokens only — not the mux alt-function table."""
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if not cons:
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return []
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pin = cons.pin_by_number(pin_num)
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if not pin or not pin.name:
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return []
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return [t.strip() for t in re.split(r"[/,]", pin.name) if t.strip()]
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def _looks_like_supply(text: str) -> bool:
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t = (text or "").strip()
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if not t:
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return False
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if _NOT_SUPPLY_RE.search(t) and not _SUPPLY_PIN_RE.search(t):
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return False
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return bool(_SUPPLY_PIN_RE.search(t) or _RAIL_PIN_RE.match(t))
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def _is_ic_supply_pin(
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graph: DesignGraph,
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cons: ComponentConstraints | None,
|
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pin_num: str,
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net_name: str,
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) -> bool:
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tokens = _pin_name_tokens(cons, pin_num)
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if tokens:
|
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return any(_looks_like_supply(t) for t in tokens)
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# No pintable row: fall back to net name / POWER type.
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if _looks_like_supply(net_name or ""):
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return True
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net = graph.nets.get(net_name)
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return bool(net and net.net_type == NetType.POWER)
|
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def _is_i2c_pin(
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graph: DesignGraph,
|
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cons: ComponentConstraints | None,
|
||||
pin_num: str,
|
||||
net_name: str,
|
||||
) -> bool:
|
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net = net_name or ""
|
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if re.match(r"(?i)SPI([_-]|$)", net) or re.search(
|
||||
r"(?i)\bSPI[_-]?(CLK|SCK|MOSI|MISO|CS|SS)\b", net,
|
||||
):
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return False
|
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tokens = _pin_name_tokens(cons, pin_num)
|
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if any(_SPI_NAME_RE.search(t) for t in tokens):
|
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return False
|
||||
if _I2C_RE.search(net):
|
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return True
|
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return any(_I2C_RE.search(t) for t in tokens)
|
||||
|
||||
|
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def _is_reset_pin(
|
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graph: DesignGraph,
|
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cons: ComponentConstraints | None,
|
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pin_num: str,
|
||||
net_name: str,
|
||||
) -> bool:
|
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if _RESET_RE.search(net_name or ""):
|
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return True
|
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return any(_RESET_RE.search(t) for t in _pin_name_tokens(cons, pin_num))
|
||||
|
||||
|
||||
def _is_ground_net(graph: DesignGraph, name: str) -> bool:
|
||||
net = graph.nets.get(name)
|
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if net and net.net_type == NetType.GROUND:
|
||||
return True
|
||||
u = name.upper().replace("-", "_")
|
||||
return u in ("GND", "VSS", "AGND", "DGND", "PGND", "GNDA", "GNDD") or (
|
||||
u.startswith("GND") or u.endswith("_GND") or u.endswith("_VSS")
|
||||
)
|
||||
|
||||
|
||||
def _is_power_net(graph: DesignGraph, name: str) -> bool:
|
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net = graph.nets.get(name)
|
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if net and net.net_type == NetType.POWER:
|
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return True
|
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return bool(re.match(r"^\d+V\d*", (name or "").upper()))
|
||||
|
||||
|
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def _capacitor_to_ground(graph: DesignGraph, power_net: str) -> bool:
|
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for ref in graph.capacitors_on_net(power_net):
|
||||
cap = graph.components[ref]
|
||||
others = {n for n in cap.pins.values() if n != power_net}
|
||||
if any(_is_ground_net(graph, n) for n in others):
|
||||
return True
|
||||
return False
|
||||
|
||||
|
||||
def _resistor_to_power(graph: DesignGraph, net_name: str) -> bool:
|
||||
for ref in graph.components_on_net(net_name):
|
||||
comp = graph.components[ref]
|
||||
if comp.component_type != ComponentType.RESISTOR:
|
||||
continue
|
||||
others = {n for n in comp.pins.values() if n != net_name}
|
||||
if any(_is_power_net(graph, n) for n in others):
|
||||
return True
|
||||
return False
|
||||
|
||||
|
||||
def _resistor_to_ground(graph: DesignGraph, net_name: str) -> bool:
|
||||
for ref in graph.components_on_net(net_name):
|
||||
comp = graph.components[ref]
|
||||
if comp.component_type != ComponentType.RESISTOR:
|
||||
continue
|
||||
others = {n for n in comp.pins.values() if n != net_name}
|
||||
if any(_is_ground_net(graph, n) for n in others):
|
||||
return True
|
||||
return False
|
||||
|
||||
|
||||
def _resistor_ohms(comp: Component) -> float | None:
|
||||
specs = comp.specs
|
||||
if isinstance(specs, ResistorSpecs) and specs.value_ohms > 0:
|
||||
return float(specs.value_ohms)
|
||||
return _parse_resistance(comp.value)
|
||||
|
||||
|
||||
def _parallel_pullup_ohms(graph: DesignGraph, net_name: str) -> float | None:
|
||||
acc = 0.0
|
||||
known = 0
|
||||
for ref in graph.components_on_net(net_name):
|
||||
comp = graph.components[ref]
|
||||
if comp.component_type != ComponentType.RESISTOR:
|
||||
continue
|
||||
others = {n for n in comp.pins.values() if n != net_name}
|
||||
if not any(_is_power_net(graph, n) for n in others):
|
||||
continue
|
||||
ohms = _resistor_ohms(comp)
|
||||
if ohms is None or ohms <= 0:
|
||||
return None
|
||||
acc += 1.0 / ohms
|
||||
known += 1
|
||||
if not known or acc <= 0:
|
||||
return None
|
||||
return 1.0 / acc
|
||||
|
||||
|
||||
def _cap_farads(comp: Component) -> float | None:
|
||||
specs = comp.specs
|
||||
if isinstance(specs, CapacitorSpecs) and specs.value_farads > 0:
|
||||
return float(specs.value_farads)
|
||||
raw = (comp.value or "").strip()
|
||||
if not raw:
|
||||
return None
|
||||
try:
|
||||
v = _parse_spice_value(raw)
|
||||
except ValueError:
|
||||
return None
|
||||
return v if v > 0 else None
|
||||
|
||||
|
||||
def _max_known_cap_farads(graph: DesignGraph, power_net: str) -> float | None:
|
||||
known: list[float] = []
|
||||
any_unknown = False
|
||||
for ref in graph.capacitors_on_net(power_net):
|
||||
cap = graph.components[ref]
|
||||
others = {n for n in cap.pins.values() if n != power_net}
|
||||
if not any(_is_ground_net(graph, n) for n in others):
|
||||
continue
|
||||
farads = _cap_farads(cap)
|
||||
if farads is None:
|
||||
any_unknown = True
|
||||
continue
|
||||
known.append(farads)
|
||||
if any_unknown or not known:
|
||||
return None
|
||||
return max(known)
|
||||
|
||||
|
||||
def _is_regulator_output_pin(
|
||||
cons: ComponentConstraints | None, pin_num: str,
|
||||
) -> bool:
|
||||
return any(_OUT_PIN_RE.search(t) for t in _pin_name_tokens(cons, pin_num))
|
||||
|
||||
|
||||
def _is_active_low_reset(
|
||||
cons: ComponentConstraints | None, pin_num: str, net_name: str,
|
||||
) -> bool:
|
||||
if _ACTIVE_LOW_RESET_RE.search(net_name or ""):
|
||||
return True
|
||||
return any(_ACTIVE_LOW_RESET_RE.search(t) for t in _pin_name_tokens(cons, pin_num))
|
||||
|
||||
|
||||
def _other_ic_on_net(graph: DesignGraph, net_name: str, self_ref: str) -> bool:
|
||||
for ref in graph.components_on_net(net_name):
|
||||
if ref == self_ref:
|
||||
continue
|
||||
other = graph.components.get(ref)
|
||||
if other and other.component_type == ComponentType.IC:
|
||||
return True
|
||||
return False
|
||||
Reference in New Issue
Block a user