Rebrand Pinscope to Periscope across product and codebase.
Rename the core package to periscopex, update UI/docs/Docker/deploy defaults to periscope.michelebigi.it, and keep legacy version/storage key aliases so existing projects keep working. Co-authored-by: Cursor <cursoragent@cursor.com>
This commit is contained in:
Cursor
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"""Topology-only functional groups for Layout F1 (routing-first floorplan).
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No millimetres. Domains = primary supply-rail clusters (not transitive
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POWER connectivity through converters); satellites = 1-hop neighbors
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classified with role_hint; layout_rules attached from IC extraction when present.
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Self-contained helpers (no import of ``validate`` / Anthropic).
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"""
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from __future__ import annotations
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import re
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from typing import Any, Literal
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from pydantic import BaseModel
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from backend.periscopex.models import (
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CapacitorSpecs,
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Component,
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ComponentConstraints,
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ComponentType,
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DesignGraph,
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NetType,
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SimpleComponentSpecs,
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)
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from backend.periscopex.resolve_passives import _parse_spice_value
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RoleHint = Literal[
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"decoupling",
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"bulk",
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"load_cap",
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"filter",
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"pullup",
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"series",
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"divider",
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"bridge",
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"crystal",
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"other",
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]
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# Roles kept in satellites / assemble_order. Unclassified "other" is dropped.
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_ASSEMBLE_ROLES = frozenset({
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"decoupling", "bulk", "load_cap", "filter", "pullup",
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"series", "divider", "bridge", "crystal",
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})
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_POWER_SAT_ROLES = frozenset({"decoupling", "bulk", "filter", "pullup"})
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_SKIP_OTHER_TYPES = frozenset({
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ComponentType.CONNECTOR,
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ComponentType.SWITCH,
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ComponentType.TEST_POINT,
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ComponentType.FIDUCIAL,
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ComponentType.MECHANICAL,
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})
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# Bias / charge-pump / bootstrap nets often stay SIGNAL in the graph.
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_BIAS_NET_RE = re.compile(
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r"(?:^|[_/\-])(REGN|PMID|BTST|BOOT|SW|LX|BST|VREG|VLDO|VREF)"
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r"(?:$|[_/\-\d])",
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re.IGNORECASE,
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)
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_STRAP_NET_RE = re.compile(
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r"(?:EN|ENABLE|RESET|NRST|BOOT|CHIP_PU|GPIO0)",
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re.IGNORECASE,
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)
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_BULK_F = 1e-6 # >= 1 µF → bulk candidate
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_XTAL_RE = re.compile(
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r"(?:^|[_/])(X(?:IN|OUT)|XTAL|OSC|HFX(?:IN|OUT)|LFX(?:IN|OUT)|CLK(?:IN|OUT)?)(?:$|[_/\d])",
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re.I,
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)
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_SUPPLY_PIN_RE = re.compile(
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r"(?:^|[_/])(VDD|VCC|VDDA|VDDD|VDDIO|DVDD|AVDD|IOVDD|VDD33|VDD18|"
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r"VIN|VBAT|VBUS|VCORE)(?:$|[_/\d])",
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re.IGNORECASE,
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)
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_RAIL_PIN_RE = re.compile(r"^(?:\+?\d+V\d*)$", re.IGNORECASE)
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_NOT_SUPPLY_RE = re.compile(
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r"\b(VSS|GND|VEE|VOUT|VREF|SW|LX|FB|BOOT|NC|VPP)\b",
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re.IGNORECASE,
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)
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_RANK_PREFIXES: list[tuple[str, int]] = [
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("ic.mcu", 0),
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("ic.mpu", 0),
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("ic.fpga", 0),
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("ic.soc", 0),
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("ic.power", 1),
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("ic.interface", 2),
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("ic.protection", 3),
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("ic.", 4),
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]
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class PlacementSatellite(BaseModel):
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ref: str
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component_type: str
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component_subtype: str | None = None
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nets: list[str] = []
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hop: int = 1
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role_hint: RoleHint = "other"
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class PlacementIcGroup(BaseModel):
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ref: str
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mpn: str | None = None
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component_subtype: str | None = None
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rank: int = 99
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nets: list[str] = []
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satellites: list[PlacementSatellite] = []
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layout_rules: list[dict[str, Any]] = []
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assemble_order: list[str] = []
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class PlacementDomain(BaseModel):
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domain_id: str
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power_nets: list[str] = []
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ic_refs: list[str] = []
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assemble_order: list[str] = []
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class FunctionalGroupsReport(BaseModel):
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"""Routing-first placement topology (no coordinates)."""
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objective: Literal["routing"] = "routing"
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domains: list[PlacementDomain] = []
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groups: list[PlacementIcGroup] = []
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def build_functional_groups(
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graph: DesignGraph,
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constraints_map: dict[str, ComponentConstraints] | None = None,
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) -> FunctionalGroupsReport:
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"""Build domains + per-IC satellite groups from the design graph."""
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cmap = constraints_map or {}
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ic_refs = [
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r for r, c in graph.components.items()
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if c.component_type == ComponentType.IC
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]
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groups: list[PlacementIcGroup] = []
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for ref in sorted(ic_refs, key=lambda r: (_ic_rank(graph.components[r]), r)):
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groups.append(_group_for_ic(graph, ref, cmap))
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domains = _build_domains(graph, ic_refs)
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by_ref = {g.ref: g for g in groups}
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for dom in domains:
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order: list[str] = []
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ranked = sorted(
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dom.ic_refs,
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key=lambda r: (by_ref[r].rank if r in by_ref else 99, r),
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)
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for iref in ranked:
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order.append(iref)
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g = by_ref.get(iref)
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if g:
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for sat in g.satellites:
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if sat.ref not in order:
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order.append(sat.ref)
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dom.assemble_order = order
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return FunctionalGroupsReport(objective="routing", domains=domains, groups=groups)
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# Alias used by the dedicated Placement pipeline (same topology artifact).
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build_placement_plan = build_functional_groups
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PlacementPlan = FunctionalGroupsReport
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def load_capacitance_farads(comp: Component) -> float | None:
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"""Crystal CL from SimpleComponentSpecs.values, if present."""
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specs = comp.specs
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if not isinstance(specs, SimpleComponentSpecs):
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return None
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raw = specs.values.get("load_capacitance_f")
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if raw is None:
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return None
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try:
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v = float(raw)
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except (TypeError, ValueError):
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return None
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return v if v > 0 else None
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def _match_constraints(
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mpn: str | None,
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datasheets: dict[str, ComponentConstraints],
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) -> ComponentConstraints | None:
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if not mpn:
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return None
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if mpn in datasheets:
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return datasheets[mpn]
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norm = re.sub(r"[/_\-\s]", "", mpn).upper()
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for ds_mpn, constraints in datasheets.items():
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if re.sub(r"[/_\-\s]", "", ds_mpn).upper() == norm:
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return constraints
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return None
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def _ic_rank(comp: Component) -> int:
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sub = (comp.component_subtype or "").lower()
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for prefix, rank in _RANK_PREFIXES:
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if sub == prefix.rstrip(".") or sub.startswith(prefix):
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return rank
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return 9
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def _group_for_ic(
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graph: DesignGraph,
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ref: str,
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cmap: dict[str, ComponentConstraints],
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) -> PlacementIcGroup:
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comp = graph.components[ref]
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cons = _match_constraints(comp.mpn or comp.value, cmap)
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nets = [n for n in graph.nets_of_component(ref) if not _is_ground_net(graph, n)]
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power_nets = {n for n in nets if _is_power_net(graph, n)}
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primary = _primary_supply_net(comp, power_nets)
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sat_map: dict[str, PlacementSatellite] = {}
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for net_name, others in graph.neighbors(ref).items():
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if _is_ground_net(graph, net_name):
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continue
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for oref in others:
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if oref == ref or oref in sat_map:
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continue
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other = graph.components.get(oref)
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if not other or other.component_type == ComponentType.IC:
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continue
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role = _role_hint(graph, comp, cons, other, net_name)
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sat_nets = {n for n in other.pins.values() if n}
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# Drop power-role parts that sit on a *different* named power rail
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# (LDO must not inherit VSYS input caps). Strap/bias caps with no
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# typed POWER net still attach.
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if role in _POWER_SAT_ROLES and primary:
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sat_power = {n for n in sat_nets if _is_power_net(graph, n)}
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if sat_power and primary not in sat_power:
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continue
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if role == "other" and other.component_type in _SKIP_OTHER_TYPES:
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continue
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if role not in _ASSEMBLE_ROLES:
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continue
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sat_map[oref] = PlacementSatellite(
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ref=oref,
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component_type=other.component_type.value,
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component_subtype=other.component_subtype,
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nets=sorted(sat_nets),
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hop=1,
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role_hint=role,
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)
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# Cap enhancement: only on the primary supply rail (when known).
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supply_nets = [primary] if primary else []
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if not supply_nets:
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supply_nets = [
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n for pin_num, n in comp.pins.items()
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if n and not _is_ground_net(graph, n)
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and _is_ic_supply_pin(graph, cons, pin_num, n)
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]
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for net_name in supply_nets:
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if not net_name or _is_ground_net(graph, net_name):
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continue
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for cref in graph.capacitors_on_net(net_name):
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if cref == ref:
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continue
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cap = graph.components.get(cref)
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if not cap:
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continue
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others = {n for n in cap.pins.values() if n != net_name}
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if not any(_is_ground_net(graph, n) for n in others):
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continue
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farads = _cap_farads(cap)
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role: RoleHint = "bulk" if farads is not None and farads >= _BULK_F else "decoupling"
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existing = sat_map.get(cref)
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if existing is None or existing.role_hint in ("other", "series"):
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sat_map[cref] = PlacementSatellite(
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ref=cref,
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component_type=cap.component_type.value,
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component_subtype=cap.component_subtype,
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nets=sorted({n for n in cap.pins.values() if n}),
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hop=1,
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role_hint=role,
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)
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satellites = sorted(sat_map.values(), key=lambda s: (_role_sort(s.role_hint), s.ref))
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assemble = [ref] + [s.ref for s in satellites]
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rules: list[dict[str, Any]] = list(cons.layout_rules) if cons and cons.layout_rules else []
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return PlacementIcGroup(
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ref=ref,
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mpn=comp.mpn,
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component_subtype=comp.component_subtype or (cons.component_subtype if cons else None),
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rank=_ic_rank(comp),
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nets=sorted(nets),
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satellites=satellites,
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layout_rules=rules,
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assemble_order=assemble,
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)
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def _role_sort(role: RoleHint) -> int:
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order = [
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"decoupling", "bulk", "load_cap", "crystal", "filter",
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"pullup", "divider", "series", "bridge", "other",
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]
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try:
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return order.index(role)
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except ValueError:
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return 99
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def _role_hint(
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graph: DesignGraph,
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ic: Component,
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cons: ComponentConstraints | None,
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other: Component,
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via_net: str,
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) -> RoleHint:
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if other.component_type == ComponentType.CRYSTAL:
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return "crystal"
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if other.component_type == ComponentType.CAPACITOR:
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if _looks_xtal_net(via_net) or _ic_pin_is_xtal(cons, via_net, ic):
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return "load_cap"
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pin_nets = {n for n in other.pins.values() if n}
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gnd_nets = {n for n in pin_nets if _is_ground_net(graph, n)}
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live = [n for n in pin_nets if n not in gnd_nets]
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ic_nets = {n for n in ic.pins.values() if n}
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# Bootstrap / flying cap between two pins of this IC.
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if len(live) == 2 and all(n in ic_nets for n in live):
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return "bridge"
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# Cap to GND on an IC pin / bias / strap / power net → local bypass.
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if gnd_nets and len(live) == 1:
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net = live[0]
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if (
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net in ic_nets
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or _is_power_net(graph, net)
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or _net_is_ic_supply(graph, ic, cons, net)
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or _BIAS_NET_RE.search(net or "")
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or _STRAP_NET_RE.search(net or "")
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):
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farads = _cap_farads(other)
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return "bulk" if farads is not None and farads >= _BULK_F else "decoupling"
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return "other"
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if other.component_type == ComponentType.INDUCTOR:
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return "filter"
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if other.component_type == ComponentType.RESISTOR:
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nets = list(dict.fromkeys(n for n in other.pins.values() if n))
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if len(nets) == 2:
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a, b = nets
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if _is_power_net(graph, a) or _is_power_net(graph, b) or (
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_BIAS_NET_RE.search(a or "") or _BIAS_NET_RE.search(b or "")
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):
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if _is_ground_net(graph, a) or _is_ground_net(graph, b):
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return "divider"
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return "pullup"
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ic_nets = set(ic.pins.values())
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if a in ic_nets and b in ic_nets:
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return "bridge"
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if a in ic_nets or b in ic_nets:
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# Set resistor / NTC leg to GND stays series (placement-local).
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return "series"
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return "other"
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return "other"
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def _looks_xtal_net(name: str) -> bool:
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return bool(_XTAL_RE.search(name or ""))
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def _ic_pin_is_xtal(
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cons: ComponentConstraints | None,
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net_name: str,
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ic: Component,
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) -> bool:
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for pin_num, n in ic.pins.items():
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if n != net_name:
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continue
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tokens = _pin_name_tokens(cons, pin_num)
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if any(_XTAL_RE.search(t) for t in tokens):
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return True
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return _looks_xtal_net(net_name)
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def _net_is_ic_supply(
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graph: DesignGraph,
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ic: Component,
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cons: ComponentConstraints | None,
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net_name: str,
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) -> bool:
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for pin_num, n in ic.pins.items():
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if n == net_name and _is_ic_supply_pin(graph, cons, pin_num, net_name):
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return True
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return _is_power_net(graph, net_name)
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|
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_UPSTREAM_BUS_RE = re.compile(
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r"(?:^|[_/\-])(VBUS|VBAT|VIN|VCHG|VAC|VPH)(?:$|[_/\-\d])",
|
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re.IGNORECASE,
|
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)
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_OUTPUT_BUS_RE = re.compile(
|
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r"(?:^|[_/\-])(VSYS|VOUT|VREG)(?:$|[_/\-\d])",
|
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re.IGNORECASE,
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)
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_REGULATED_RAIL_RE = re.compile(r"^\+?\d+V\d*", re.IGNORECASE)
|
||||
|
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def _primary_supply_net(comp: Component, power_nets: set[str]) -> str | None:
|
||||
"""Pick one supply rail per IC so converters do not merge the whole board.
|
||||
|
||||
Consumers prefer regulated digital rails (3V3 / VDD). Power ICs prefer
|
||||
output-ish nets (VSYS / VOUT / regulated) over upstream buses (VBUS / VIN).
|
||||
"""
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||||
if not power_nets:
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return None
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||||
|
||||
sub = (comp.component_subtype or "").lower()
|
||||
is_power_ic = sub.startswith("ic.power")
|
||||
|
||||
def score(name: str) -> tuple[int, str]:
|
||||
u = name.upper()
|
||||
s = 0
|
||||
if _UPSTREAM_BUS_RE.search(u):
|
||||
s -= 100
|
||||
if _OUTPUT_BUS_RE.search(u):
|
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s += 50
|
||||
if _REGULATED_RAIL_RE.match(u):
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s += 40
|
||||
if "3V3" in u or "3.3V" in u:
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s += 25
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elif re.search(r"1V\d+|1\.?\d+V", u):
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s += 10 # core rails still regulated, but secondary to I/O
|
||||
if "VDD" in u or "VCC" in u:
|
||||
s += 15
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if is_power_ic:
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if _UPSTREAM_BUS_RE.search(u):
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s -= 40
|
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if _OUTPUT_BUS_RE.search(u) or _REGULATED_RAIL_RE.match(u):
|
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s += 30
|
||||
return (s, name)
|
||||
|
||||
return max(power_nets, key=score)
|
||||
|
||||
|
||||
def _domain_id_for_rail(rail: str) -> str:
|
||||
safe = re.sub(r"[^A-Za-z0-9]+", "_", rail or "").strip("_")
|
||||
return f"domain_{safe}" if safe else "domain_unknown"
|
||||
|
||||
|
||||
def _build_domains(graph: DesignGraph, ic_refs: list[str]) -> list[PlacementDomain]:
|
||||
"""Cluster ICs by primary supply rail (not union-find across converters)."""
|
||||
power_by_ic: dict[str, set[str]] = {}
|
||||
for ref in ic_refs:
|
||||
nets: set[str] = set()
|
||||
for n in graph.nets_of_component(ref):
|
||||
if _is_power_net(graph, n) and not _is_ground_net(graph, n):
|
||||
nets.add(n)
|
||||
power_by_ic[ref] = nets
|
||||
|
||||
by_rail: dict[str, list[str]] = {}
|
||||
no_rail: list[str] = []
|
||||
for ref in ic_refs:
|
||||
primary = _primary_supply_net(graph.components[ref], power_by_ic[ref])
|
||||
if primary is None:
|
||||
no_rail.append(ref)
|
||||
else:
|
||||
by_rail.setdefault(primary, []).append(ref)
|
||||
|
||||
domains: list[PlacementDomain] = []
|
||||
for rail, members in sorted(by_rail.items(), key=lambda x: x[0].upper()):
|
||||
domains.append(PlacementDomain(
|
||||
domain_id=_domain_id_for_rail(rail),
|
||||
power_nets=[rail],
|
||||
ic_refs=sorted(members),
|
||||
))
|
||||
if no_rail:
|
||||
domains.append(PlacementDomain(
|
||||
domain_id="domain_unpowered",
|
||||
power_nets=[],
|
||||
ic_refs=sorted(no_rail),
|
||||
))
|
||||
return domains
|
||||
|
||||
|
||||
def _pin_name_tokens(cons: ComponentConstraints | None, pin_num: str) -> list[str]:
|
||||
if not cons:
|
||||
return []
|
||||
pin = cons.pin_by_number(pin_num)
|
||||
if not pin or not pin.name:
|
||||
return []
|
||||
return [t.strip() for t in re.split(r"[/,]", pin.name) if t.strip()]
|
||||
|
||||
|
||||
def _looks_like_supply(text: str) -> bool:
|
||||
t = (text or "").strip()
|
||||
if not t:
|
||||
return False
|
||||
if _NOT_SUPPLY_RE.search(t) and not _SUPPLY_PIN_RE.search(t):
|
||||
return False
|
||||
return bool(_SUPPLY_PIN_RE.search(t) or _RAIL_PIN_RE.match(t))
|
||||
|
||||
|
||||
def _is_ic_supply_pin(
|
||||
graph: DesignGraph,
|
||||
cons: ComponentConstraints | None,
|
||||
pin_num: str,
|
||||
net_name: str,
|
||||
) -> bool:
|
||||
tokens = _pin_name_tokens(cons, pin_num)
|
||||
if tokens:
|
||||
return any(_looks_like_supply(t) for t in tokens)
|
||||
if _looks_like_supply(net_name or ""):
|
||||
return True
|
||||
net = graph.nets.get(net_name)
|
||||
return bool(net and net.net_type == NetType.POWER)
|
||||
|
||||
|
||||
def _is_ground_net(graph: DesignGraph, name: str) -> bool:
|
||||
net = graph.nets.get(name)
|
||||
if net and net.net_type == NetType.GROUND:
|
||||
return True
|
||||
u = name.upper().replace("-", "_")
|
||||
return u in ("GND", "VSS", "AGND", "DGND", "PGND", "GNDA", "GNDD") or (
|
||||
u.startswith("GND") or u.endswith("_GND") or u.endswith("_VSS")
|
||||
)
|
||||
|
||||
|
||||
def _is_power_net(graph: DesignGraph, name: str) -> bool:
|
||||
net = graph.nets.get(name)
|
||||
if net and net.net_type == NetType.POWER:
|
||||
return True
|
||||
return bool(re.match(r"^\+?\d+V\d*", (name or "").upper()))
|
||||
|
||||
|
||||
def _cap_farads(comp: Component) -> float | None:
|
||||
specs = comp.specs
|
||||
if isinstance(specs, CapacitorSpecs) and specs.value_farads > 0:
|
||||
return float(specs.value_farads)
|
||||
raw = (comp.value or "").strip()
|
||||
if not raw:
|
||||
return None
|
||||
try:
|
||||
v = _parse_spice_value(raw)
|
||||
except ValueError:
|
||||
return None
|
||||
return v if v > 0 else None
|
||||
Reference in New Issue
Block a user