Rewrite DesignGraph builder as original Periscope graph.py.
Src module classifies refs, infers net type/voltage, and prefers board nets when a .kicad_pcb is present. PinScope graph.py remains in dependency/.
This commit is contained in:
@@ -0,0 +1,367 @@
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"""Build a Periscope DesignGraph from netlist, BOM, datasheets, and optional PCB.
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This is original Periscope orchestration. Inherited PinScope ``graph.py`` stays
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in ``periscope/dependency/`` until this module is the live winner.
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"""
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from __future__ import annotations
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import json
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import re
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from pathlib import Path
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from backend.periscopex.models import (
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CadIndexEntry,
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Component,
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ComponentConstraints,
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ComponentModel,
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ComponentSpecs,
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ComponentType,
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DesignGraph,
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Net,
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NetType,
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PinConnection,
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SimpleComponentSpecs,
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)
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from backend.periscopex.parsers import parse_bom, parse_netlist_any
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from backend.periscopex.resolve_passives import SkippedItem, resolve_bom, resolved_to_specs
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from backend.periscopex.utils import safe_mpn
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# Ref-des prefix → type. Longer prefixes must be checked first (LED before L).
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_REF_PREFIXES: tuple[tuple[str, ComponentType], ...] = (
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("LED", ComponentType.DISCRETE),
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("RN", ComponentType.RESISTOR),
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("FB", ComponentType.INDUCTOR),
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("SW", ComponentType.SWITCH),
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("TP", ComponentType.TEST_POINT),
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("IC", ComponentType.IC),
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("MH", ComponentType.MECHANICAL),
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("FM", ComponentType.FIDUCIAL),
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("R", ComponentType.RESISTOR),
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("C", ComponentType.CAPACITOR),
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("L", ComponentType.INDUCTOR),
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("U", ComponentType.IC),
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("J", ComponentType.CONNECTOR),
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("X", ComponentType.CRYSTAL),
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("Y", ComponentType.CRYSTAL),
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("D", ComponentType.DISCRETE),
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("Q", ComponentType.DISCRETE),
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("T", ComponentType.TRANSFORMER),
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("F", ComponentType.FUSE),
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)
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_FOOTPRINT_HINTS: tuple[tuple[re.Pattern[str], ComponentType], ...] = (
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(re.compile(
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r"(?i)(?:^|[\s_])("
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r"CONN(?:_|\b)|TERM(?:\b|_BLK)|HEADER|SOCKET|JACK|RECEPTACLE|PLUG|"
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r"SCREW\s*TERM|PINHEADER|BARREL|BANANA|XT30|XT60|XT90|USB|"
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r"WURTH\s*746\d|TE\s*282834|TE\s*2828\d|MOLEX|JST"
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r")"
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), ComponentType.CONNECTOR),
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(re.compile(r"(?i)TestPoint|TEST[_\s]POINT|\bTP_"), ComponentType.TEST_POINT),
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(re.compile(r"(?i)^LED[\s_]|\bLED\s+\d{3,4}"), ComponentType.DISCRETE),
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(re.compile(r"(?i)^CAP[\s_]|\bCAP_|CAPACITOR"), ComponentType.CAPACITOR),
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(re.compile(r"(?i)^RES[\s_]|\bRES_|RESISTOR"), ComponentType.RESISTOR),
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(re.compile(r"(?i)^IND[\s_]|\bIND_|INDUCTOR"), ComponentType.INDUCTOR),
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(re.compile(r"(?i)DO214|DO220|SOD\d|SMD?J5|SMB_|SOT-?23"), ComponentType.DISCRETE),
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)
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_POWER_PREFIXES = (
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"VCC", "VDD", "VBUS", "VBAT", "VSYS", "VSUP", "VPWR",
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"AVDD", "DVDD", "AVCC", "DVCC", "PVDD", "PVCC",
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"V_",
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)
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_GROUND_NAMES = {"GND", "AGND", "DGND", "PGND", "VSS", "AVSS", "DVSS", "PVSS"}
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_GROUND_SUFFIXES = ("_GND", "GND")
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def _classify_component(ref: str, footprint: str) -> ComponentType:
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letters = re.match(r"^[A-Za-z]+", ref)
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if letters:
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token = letters.group().upper()
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for prefix, ctype in _REF_PREFIXES:
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if token == prefix or token.startswith(prefix):
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# Require exact prefix match on the letter run (RN not R).
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if token == prefix:
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return ctype
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for prefix, ctype in _REF_PREFIXES:
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if token == prefix:
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return ctype
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fp = footprint or ""
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for pattern, ctype in _FOOTPRINT_HINTS:
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if pattern.search(fp):
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return ctype
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return ComponentType.UNKNOWN
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def _parse_rail_voltage(name: str) -> float | None:
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m = re.match(r"^\+(\d+)V(\d+)$", name)
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if m:
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return float(f"{m.group(1)}.{m.group(2)}")
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m = re.match(r"^\+(\d+(?:\.\d+)?)V$", name)
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if m:
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return float(m.group(1))
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m = re.search(r"(\d+)V(\d+)", name)
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if m:
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return float(f"{m.group(1)}.{m.group(2)}")
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m = re.search(r"(\d+(?:\.\d+)?)V(?:\d|$|_)", name)
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if m:
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return float(m.group(1))
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return None
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def _infer_net_properties(name: str) -> tuple[NetType, float | None]:
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upper = name.upper()
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if upper in _GROUND_NAMES or any(upper.endswith(s) for s in _GROUND_SUFFIXES):
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return NetType.GROUND, 0.0
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if name.startswith("+"):
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return NetType.POWER, _parse_rail_voltage(name)
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if any(upper.startswith(p) for p in _POWER_PREFIXES):
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return NetType.POWER, _parse_rail_voltage(name)
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if re.match(r"^\d+V\d*", upper):
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return NetType.POWER, _parse_rail_voltage(name)
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return NetType.SIGNAL, None
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def _norm_mpn(s: str) -> str:
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return re.sub(r"[/_\-\s]", "", s).upper()
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def _load_datasheets(directory: str | Path) -> dict[str, tuple[Path, ComponentConstraints]]:
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result: dict[str, tuple[Path, ComponentConstraints]] = {}
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dirpath = Path(directory)
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if not dirpath.is_dir():
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return result
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for json_file in dirpath.glob("*.json"):
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raw = json.loads(json_file.read_text())
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constraints = ComponentConstraints.model_validate(raw)
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result[constraints.mpn] = (json_file, constraints)
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return result
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def _match_datasheet(
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mpn: str | None,
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datasheets: dict[str, tuple[Path, ComponentConstraints]],
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) -> tuple[Path | None, ComponentConstraints | None]:
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if not mpn:
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return None, None
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if mpn in datasheets:
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return datasheets[mpn]
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want = _norm_mpn(mpn)
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for ds_mpn, hit in datasheets.items():
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if _norm_mpn(ds_mpn) == want:
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return hit
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return None, None
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def _load_component_models(directory: str | Path) -> dict[str, ComponentSpecs]:
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result: dict[str, ComponentSpecs] = {}
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dirpath = Path(directory)
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if not dirpath.is_dir():
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return result
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for json_file in dirpath.glob("*.json"):
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raw = json.loads(json_file.read_text())
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model = ComponentModel.model_validate(raw)
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result[model.mpn] = model.specs
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return result
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def _save_component_model(mpn: str, specs: ComponentSpecs, directory: Path) -> None:
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directory.mkdir(parents=True, exist_ok=True)
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model = ComponentModel(mpn=mpn, specs=specs)
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(directory / f"{safe_mpn(mpn)}.json").write_text(
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model.model_dump_json(indent=2) + "\n"
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)
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def _bom_rows(bom: dict) -> dict[str, dict]:
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out: dict[str, dict] = {}
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for ref, entry in bom.items():
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row = {"mpn": entry.get("mpn"), "value": entry.get("value", "")}
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if "dnp" in entry:
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row["dnp"] = entry.get("dnp")
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if entry.get("variant") is not None:
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row["variant"] = entry.get("variant")
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out[ref] = row
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return out
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def _apply_pcb_nets(pcb_path: Path, parts: dict, raw_nets: dict) -> tuple[dict, dict]:
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from backend.periscopex.parsers_kicad_pcb import nets_from_pcb, parse_kicad_pcb
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layout = parse_kicad_pcb(pcb_path)
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pcb_nets = nets_from_pcb(layout)
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if not pcb_nets:
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return parts, raw_nets
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for ref, fp in layout.footprints.items():
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parts.setdefault(ref, fp.footprint or "")
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return parts, pcb_nets
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def _merge_kicad_fields(netlist_path: Path, bom: dict) -> dict[str, dict]:
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from backend.periscopex.parsers_kicad import kicad_part_fields
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schematic_fields: dict[str, dict] = {}
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for ref, extra in kicad_part_fields(netlist_path).items():
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schematic_fields[ref] = {
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"mpn": extra.get("mpn"),
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"value": extra.get("value", ""),
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"cad_uuid": extra.get("cad_uuid") or "",
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"cad_sheet": extra.get("cad_sheet") or "",
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}
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entry = bom.setdefault(
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ref,
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{"value": "", "footprint": "", "mpn": None, "lcsc": None, "datasheet_url": None},
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)
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if extra.get("mpn") and (not entry.get("mpn") or entry.get("mpn") == entry.get("value")):
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entry["mpn"] = extra["mpn"]
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if extra.get("lcsc") and not entry.get("lcsc"):
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entry["lcsc"] = extra["lcsc"]
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if extra.get("value") and not entry.get("value"):
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entry["value"] = extra["value"]
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if extra.get("footprint") and not entry.get("footprint"):
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entry["footprint"] = extra["footprint"]
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return schematic_fields
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def _pin_name_for(
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ref: str,
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pin_num: str,
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constraints_by_ref: dict[str, ComponentConstraints],
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components: dict[str, Component],
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mpn_specs: dict[str, ComponentSpecs],
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) -> str | None:
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constraints = constraints_by_ref.get(ref)
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if constraints:
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pin_obj = constraints.pin_by_number(pin_num)
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return pin_obj.name if pin_obj else None
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comp = components.get(ref)
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if not comp or not comp.mpn:
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return None
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specs = mpn_specs.get(comp.mpn)
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if isinstance(specs, SimpleComponentSpecs) and specs.pintable:
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pin_obj = specs.pin_by_number(pin_num)
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return pin_obj.name if pin_obj else None
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return None
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def build_graph(
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netlist_path: str | Path,
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bom_path: str | Path,
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datasheets_dir: str | Path = "datasheets/extracted",
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patterns_dir: str | Path = "component-patterns",
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component_models_dir: str | Path = "component-models",
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*,
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reference_col: str = "Reference",
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mpn_col: str = "Manufacturer Part Number",
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skipped: list[SkippedItem] | None = None,
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include_subdesigns: set[str] | None = None,
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pcb_path: str | Path | None = None,
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) -> DesignGraph:
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"""Deterministic graph: BOM → netlist → optional board nets → datasheets → DesignGraph."""
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bom = parse_bom(bom_path, reference_col=reference_col, mpn_col=mpn_col)
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bom_fields = _bom_rows(bom)
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parts, raw_nets, fmt = parse_netlist_any(
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netlist_path,
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known_refs=set(bom.keys()),
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include_subdesigns=include_subdesigns,
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)
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if pcb_path is not None:
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pcb = Path(pcb_path)
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if pcb.is_file():
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parts, raw_nets = _apply_pcb_nets(pcb, parts, raw_nets)
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schematic_fields: dict[str, dict] = {}
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if fmt.startswith("kicad"):
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schematic_fields = _merge_kicad_fields(Path(netlist_path), bom)
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datasheets = _load_datasheets(datasheets_dir)
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models_dir = Path(component_models_dir)
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mpn_specs: dict[str, ComponentSpecs] = _load_component_models(models_dir)
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mpn_subtype: dict[str, str] = {}
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for rp in resolve_bom(
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bom_path, patterns_dir, reference_col=reference_col, mpn_col=mpn_col, skipped=skipped
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):
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if rp.component_subtype:
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mpn_subtype[rp.mpn] = rp.component_subtype
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if rp.mpn in mpn_specs:
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continue
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try:
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specs = resolved_to_specs(rp)
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mpn_specs[rp.mpn] = specs
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_save_component_model(rp.mpn, specs, models_dir)
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except Exception as e:
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if skipped is not None:
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skipped.append(SkippedItem(rp.mpn, "passive_specs", str(e)))
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if not parts:
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net_refs = {ref for pins in raw_nets.values() for ref, _ in pins}
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parts = {ref: bom.get(ref, {}).get("footprint", "") for ref in (set(bom) | net_refs)}
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components: dict[str, Component] = {}
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for ref, footprint in parts.items():
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bom_entry = bom.get(ref, {})
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value = bom_entry.get("value", "")
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mpn = bom_entry.get("mpn") or None
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ctype = _classify_component(ref, footprint)
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if not mpn and ctype == ComponentType.IC:
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mpn = (value or "").strip() or None
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components[ref] = Component(
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reference=ref,
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value=value,
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footprint=footprint,
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component_type=ctype,
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mpn=mpn,
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pins={},
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)
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constraints_by_ref: dict[str, ComponentConstraints] = {}
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for ref, comp in components.items():
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if not comp.mpn:
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continue
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_, constraints = _match_datasheet(comp.mpn, datasheets)
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if constraints:
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constraints_by_ref[ref] = constraints
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if constraints.component_subtype:
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comp.component_subtype = constraints.component_subtype
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if comp.mpn in mpn_specs:
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comp.specs = mpn_specs[comp.mpn]
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if not comp.component_subtype:
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specs = mpn_specs[comp.mpn]
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subtype = getattr(specs, "component_subtype", None)
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if subtype:
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comp.component_subtype = subtype
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if not comp.component_subtype and comp.mpn in mpn_subtype:
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comp.component_subtype = mpn_subtype[comp.mpn]
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nets: dict[str, Net] = {}
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for net_name, pin_list in raw_nets.items():
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net_type, voltage = _infer_net_properties(net_name)
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pin_connections: list[PinConnection] = []
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for ref, pin_num in pin_list:
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if ref in components:
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components[ref].pins[pin_num] = net_name
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pin_connections.append(PinConnection(
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component_ref=ref,
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pin_number=pin_num,
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pin_name=_pin_name_for(ref, pin_num, constraints_by_ref, components, mpn_specs),
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))
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nets[net_name] = Net(
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name=net_name, net_type=net_type, voltage=voltage, pins=pin_connections
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)
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cad_index: dict[str, CadIndexEntry] = {}
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for ref, extra in schematic_fields.items():
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uuid = extra.get("cad_uuid") or ""
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sheet = extra.get("cad_sheet") or ""
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if uuid or sheet:
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cad_index[ref] = CadIndexEntry(uuid=uuid, sheet=sheet)
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return DesignGraph(
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components=components,
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nets=nets,
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bom_fields=bom_fields,
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schematic_fields=schematic_fields,
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cad_index=cad_index,
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)
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@@ -0,0 +1,50 @@
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"""Native graph builder lives in periscope/src; via≠pad stays on the KiCad PCB parser."""
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from __future__ import annotations
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from pathlib import Path
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import backend.periscopex.graph as graph
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from backend.periscopex.graph import _classify_component, _infer_net_properties
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from backend.periscopex.models import ComponentType, NetType
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from backend.periscopex.parsers_kicad_pcb import LayoutPad, LayoutVia
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def test_graph_module_is_src_rewrite():
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path = Path(graph.__file__).resolve()
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assert path.parts[-5:] == ("periscope", "src", "backend", "periscopex", "graph.py")
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text = path.read_text(encoding="utf-8")
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assert "Native Periscope overlay" not in text
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assert "original Periscope orchestration" in text
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def test_classify_prefixes_and_unknown():
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assert _classify_component("FB1", "") == ComponentType.INDUCTOR
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assert _classify_component("RN4", "") == ComponentType.RESISTOR
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assert _classify_component("F1", "") == ComponentType.FUSE
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assert _classify_component("R10", "") == ComponentType.RESISTOR
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assert _classify_component("9", "") == ComponentType.UNKNOWN
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assert _classify_component("9", "CONN_HEADER") == ComponentType.CONNECTOR
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def test_infer_ground_power_signal():
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assert _infer_net_properties("GND") == (NetType.GROUND, 0.0)
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assert _infer_net_properties("AGND") == (NetType.GROUND, 0.0)
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ntype, volts = _infer_net_properties("+3V3")
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assert ntype == NetType.POWER
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assert volts == 3.3
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ntype, volts = _infer_net_properties("3V3_DIGITAL")
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assert ntype == NetType.POWER
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assert volts == 3.3
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ntype, volts = _infer_net_properties("I2C1_SCL")
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assert ntype == NetType.SIGNAL
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assert volts is None
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def test_via_is_not_pad():
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via = LayoutVia(x=0.0, y=0.0, net="GND", drill=0.3)
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pad = LayoutPad(number="1", x=0.0, y=0.0, net="GND")
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assert type(via) is not type(pad)
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assert not hasattr(via, "number")
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||||
assert pad.number == "1"
|
||||
assert via.net == "GND"
|
||||
Reference in New Issue
Block a user