Stamp 2.60.0 incomplete PCB exam and owner project delete.

Partial layouts still use MODE=pcb. Missing copper is INSUFFICIENT or
skipped, never Euclidean stand-in tracks. Via≠Pad unchanged. DELETE
/api/projects/{id} is owner-only with a dashboard confirm dialog.

tests/test_pcb_review.py

@@ -173,11 +173,15 @@ def test_missing_footprint_is_pe_lay_002():
 
 def test_run_pcb_checks_assigns_pcb_ids_and_recommendations():
     from tests.test_placement_check import _xtal_cons, _x1_c9_layout
+    from backend.periscopex.models import LayoutSegment
 
+    segs = [
+        LayoutSegment(start=(0.0, 0.0), end=(10.0, 0.0), width=0.2, layer="F.Cu", net="/HFXIN"),
+    ]
     findings = run_pcb_checks(
         _graph(),
         _xtal_cons(max_distance_mm=2.0),
-        _x1_c9_layout(cap_x=10.0),
+        _x1_c9_layout(cap_x=10.0, segments=segs),
     )
     plc = [f for f in findings if f.rule_id == "PE-PLC-001"]
     assert plc
@@ -187,11 +191,15 @@ def test_run_pcb_checks_assigns_pcb_ids_and_recommendations():
 
 def test_close_decoupling_has_no_plc_001():
     from tests.test_placement_check import _xtal_cons, _x1_c9_layout
+    from backend.periscopex.models import LayoutSegment
 
+    segs = [
+        LayoutSegment(start=(0.0, 0.0), end=(0.5, 0.0), width=0.2, layer="F.Cu", net="/HFXIN"),
+    ]
     findings = run_pcb_checks(
         _graph(),
         _xtal_cons(max_distance_mm=2.0),
-        _x1_c9_layout(cap_x=0.5),
+        _x1_c9_layout(cap_x=0.5, segments=segs),
     )
     assert all(f.rule_id != "PE-PLC-001" for f in findings)