Add power-margin, PG-to-EN sequencing, and DNP enable checks.
Compare only specified IQ plus I_load to Iout_max and series-R drop, flag sequencing only when power_sequence is in specs, and treat DNP as a fitted-variant graph so a missing enable pull is ERROR only when the BOM actually marks DNP. Co-authored-by: Cursor <cursoragent@cursor.com>
This commit is contained in:
Cursor
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"""DNP variant: fitted enable without pull/driver is ERROR."""
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from __future__ import annotations
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from pathlib import Path
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from backend.pinscopex.dnp_check import check_dnp_enables
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from backend.pinscopex.models import (
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Component,
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ComponentConstraints,
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ComponentType,
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DesignGraph,
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Net,
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NetType,
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Pin,
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PinConnection,
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ResistorSpecs,
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)
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from backend.pinscopex.parsers import parse_bom
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def _graph(components, nets, bom_fields=None):
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net_objs = {
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name: Net(
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name=name, net_type=ntype,
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pins=[PinConnection(component_ref=r, pin_number=str(p)) for r, p in conns],
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)
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for name, (ntype, conns) in nets.items()
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}
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return DesignGraph(components=components, nets=net_objs, bom_fields=bom_fields or {})
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def _cons():
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return {
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"LDOX": ComponentConstraints(
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mpn="LDOX",
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pintable=[
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Pin(number=1, name="VIN"),
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Pin(number=2, name="VOUT"),
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Pin(number=3, name="EN"),
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Pin(number=4, name="GND"),
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],
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absolute_maximum_ratings=[], rules=[],
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)
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}
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def _ldo():
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return Component(
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reference="U1", value="", footprint="",
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component_type=ComponentType.IC, mpn="LDOX",
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pins={"1": "VIN", "2": "VOUT", "3": "EN_NET", "4": "GND"},
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)
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def _r(dnp_net="EN_NET"):
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return Component(
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reference="R1", value="10k", footprint="",
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component_type=ComponentType.RESISTOR, mpn="R1",
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pins={"1": dnp_net, "2": "VIN"},
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specs=ResistorSpecs(value_ohms=10000, value_formatted="10k"),
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)
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def test_dnp_pull_leaves_enable_floating():
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g = _graph(
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{"U1": _ldo(), "R1": _r()},
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{
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"VIN": (NetType.POWER, [("U1", "1"), ("R1", "2")]),
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"VOUT": (NetType.POWER, [("U1", "2")]),
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"EN_NET": (NetType.SIGNAL, [("U1", "3"), ("R1", "1")]),
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"GND": (NetType.GROUND, [("U1", "4")]),
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},
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bom_fields={
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"U1": {"mpn": "LDOX", "value": "", "dnp": False},
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"R1": {"mpn": "R1", "value": "10k", "dnp": True},
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},
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)
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findings = check_dnp_enables(g, _cons())
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assert len(findings) == 1
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assert findings[0].rule_id == "PS-DNP-001"
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assert findings[0].status == "ERROR"
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def test_fitted_pull_is_silent():
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g = _graph(
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{"U1": _ldo(), "R1": _r()},
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{
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"VIN": (NetType.POWER, [("U1", "1"), ("R1", "2")]),
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"VOUT": (NetType.POWER, [("U1", "2")]),
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"EN_NET": (NetType.SIGNAL, [("U1", "3"), ("R1", "1")]),
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"GND": (NetType.GROUND, [("U1", "4")]),
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},
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bom_fields={
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"U1": {"mpn": "LDOX", "value": "", "dnp": False},
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"R1": {"mpn": "R1", "value": "10k", "dnp": False},
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},
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)
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assert check_dnp_enables(g, _cons()) == []
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def test_no_dnp_column_skips_floating_enable():
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g = _graph(
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{"U1": _ldo()},
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{
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"VIN": (NetType.POWER, [("U1", "1")]),
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"VOUT": (NetType.POWER, [("U1", "2")]),
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"EN_NET": (NetType.SIGNAL, [("U1", "3")]),
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"GND": (NetType.GROUND, [("U1", "4")]),
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},
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bom_fields={"U1": {"mpn": "LDOX", "value": ""}},
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)
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assert check_dnp_enables(g, _cons()) == []
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def test_parse_bom_reads_dnp_and_skips_when_column_absent(tmp_path: Path):
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with_dnp = tmp_path / "dnp.csv"
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with_dnp.write_text(
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"Reference,Value,DNP,Manufacturer Part Number\n"
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"U1,LDO,,LDOX\n"
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"R1,10k,1,Rpull\n"
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)
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bom = parse_bom(with_dnp)
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assert bom["U1"]["dnp"] is False
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assert bom["R1"]["dnp"] is True
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no_col = tmp_path / "plain.csv"
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no_col.write_text("Reference,Value,Manufacturer Part Number\nU1,LDO,LDOX\n")
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bom2 = parse_bom(no_col)
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assert "dnp" not in bom2["U1"]
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@@ -0,0 +1,124 @@
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"""Regulator Iout margin and series-R IR drop — no invented IQ or traces."""
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from __future__ import annotations
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from backend.pinscopex.models import (
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Component,
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ComponentConstraints,
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ComponentType,
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DesignGraph,
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Net,
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NetType,
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Pin,
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PinConnection,
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ResistorSpecs,
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SimpleComponentSpecs,
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)
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from backend.pinscopex.power_margin_check import check_power_margin
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def _graph(components, nets):
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net_objs = {}
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for name, (ntype, volt, conns) in nets.items():
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net_objs[name] = Net(
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name=name, net_type=ntype, voltage=volt,
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pins=[PinConnection(component_ref=r, pin_number=str(p)) for r, p in conns],
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)
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return DesignGraph(components=components, nets=net_objs)
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def _cons():
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return {
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"LDOX": ComponentConstraints(
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mpn="LDOX", component_subtype="ic.power.ldo",
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pintable=[
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Pin(number=1, name="VIN"),
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Pin(number=2, name="VOUT"),
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Pin(number=3, name="GND"),
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],
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absolute_maximum_ratings=[], rules=[],
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)
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}
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def _ldo(values):
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return Component(
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reference="U1", value="", footprint="",
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component_type=ComponentType.IC, component_subtype="ic.power.ldo",
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mpn="LDOX",
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pins={"1": "VIN", "2": "VOUT", "3": "GND"},
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specs=SimpleComponentSpecs(specs_type="ic", component_subtype="ic.power.ldo", values=values),
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)
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def _mcu(iq=None):
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values = {} if iq is None else {"iq_a": iq}
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return Component(
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reference="U2", value="", footprint="",
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component_type=ComponentType.IC, mpn="MCU",
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pins={"1": "VOUT", "2": "GND"},
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specs=SimpleComponentSpecs(specs_type="ic", values=values) if values else None,
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)
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def test_load_over_iout_max_is_ps_pwr_001():
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g = _graph(
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{
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"U1": _ldo({"i_load_a": 0.4, "iout_max_a": 0.5}),
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"U2": _mcu(0.2),
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},
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{
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"VIN": (NetType.POWER, 5.0, [("U1", "1")]),
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"VOUT": (NetType.POWER, 3.3, [("U1", "2"), ("U2", "1")]),
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"GND": (NetType.GROUND, 0.0, [("U1", "3"), ("U2", "2")]),
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},
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)
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findings = check_power_margin(g, _cons())
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assert any(f.rule_id == "PS-PWR-001" and f.designator == "U1" for f in findings)
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def test_missing_iq_is_not_guessed_into_margin_fail():
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g = _graph(
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{
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"U1": _ldo({"iout_max_a": 0.1}),
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"U2": _mcu(None),
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},
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{
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"VIN": (NetType.POWER, 5.0, [("U1", "1")]),
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"VOUT": (NetType.POWER, 3.3, [("U1", "2"), ("U2", "1")]),
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"GND": (NetType.GROUND, 0.0, [("U1", "3"), ("U2", "2")]),
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},
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)
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assert check_power_margin(g, _cons()) == []
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def test_series_r_ir_drop_uses_i_load_not_trace():
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r = Component(
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reference="R1", value="1", footprint="",
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component_type=ComponentType.RESISTOR, mpn="R1",
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pins={"1": "USB", "2": "VIN"},
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specs=ResistorSpecs(value_ohms=1.0, value_formatted="1"),
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)
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g = _graph(
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{"U1": _ldo({"i_load_a": 0.5, "iout_max_a": 1.0}), "R1": r},
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{
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"USB": (NetType.POWER, 5.0, [("R1", "1")]),
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"VIN": (NetType.POWER, 5.0, [("R1", "2"), ("U1", "1")]),
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"VOUT": (NetType.POWER, 3.3, [("U1", "2")]),
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"GND": (NetType.GROUND, 0.0, [("U1", "3")]),
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},
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)
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findings = check_power_margin(g, _cons())
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assert any(f.designator == "R1" and f.rule_id == "PS-PWR-001" for f in findings)
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def test_no_series_r_does_not_invent_trace_drop():
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g = _graph(
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{"U1": _ldo({"i_load_a": 0.5, "iout_max_a": 1.0})},
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{
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"VIN": (NetType.POWER, 5.0, [("U1", "1")]),
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"VOUT": (NetType.POWER, 3.3, [("U1", "2")]),
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"GND": (NetType.GROUND, 0.0, [("U1", "3")]),
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},
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)
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assert check_power_margin(g, _cons()) == []
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@@ -0,0 +1,91 @@
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"""PG→EN sequencing only when power_sequence is in IC specs."""
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from __future__ import annotations
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from backend.pinscopex.models import (
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Component,
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ComponentConstraints,
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ComponentType,
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DesignGraph,
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Net,
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NetType,
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Pin,
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PinConnection,
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SimpleComponentSpecs,
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)
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from backend.pinscopex.sequencing_check import check_power_sequencing
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def _graph(components, nets):
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net_objs = {
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name: Net(
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name=name, net_type=ntype,
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pins=[PinConnection(component_ref=r, pin_number=str(p)) for r, p in conns],
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)
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for name, (ntype, conns) in nets.items()
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}
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return DesignGraph(components=components, nets=net_objs)
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def _cons():
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return {
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"L1": ComponentConstraints(
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mpn="L1", component_subtype="ic.power.ldo",
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pintable=[
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Pin(number=1, name="VIN"), Pin(number=2, name="VOUT"),
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Pin(number=3, name="PG"), Pin(number=4, name="GND"),
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],
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absolute_maximum_ratings=[], rules=[],
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),
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"L2": ComponentConstraints(
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mpn="L2", component_subtype="ic.power.ldo",
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pintable=[
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Pin(number=1, name="VIN"), Pin(number=2, name="VOUT"),
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Pin(number=3, name="EN"), Pin(number=4, name="GND"),
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],
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absolute_maximum_ratings=[], rules=[],
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),
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}
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def _ldo(ref, mpn, pins, values=None):
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return Component(
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reference=ref, value="", footprint="",
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component_type=ComponentType.IC, component_subtype="ic.power.ldo",
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mpn=mpn, pins=pins,
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specs=SimpleComponentSpecs(
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specs_type="ic", component_subtype="ic.power.ldo", values=values or {},
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),
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)
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def _dual(pg_net, en_net, sequence=True):
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u1 = _ldo("U1", "L1", {"1": "5V", "2": "3V3", "3": pg_net, "4": "GND"})
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vals = {"power_sequence": "pg_before_en"} if sequence else {}
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u2 = _ldo("U2", "L2", {"1": "3V3", "2": "1V8", "3": en_net, "4": "GND"}, vals)
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return _graph(
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{"U1": u1, "U2": u2},
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{
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"5V": (NetType.POWER, [("U1", "1")]),
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"3V3": (NetType.POWER, [("U1", "2"), ("U2", "1")]),
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"1V8": (NetType.POWER, [("U2", "2")]),
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pg_net: (NetType.SIGNAL, [("U1", "3")] + ([("U2", "3")] if pg_net == en_net else [])),
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**({en_net: (NetType.SIGNAL, [("U2", "3")])} if pg_net != en_net else {}),
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"GND": (NetType.GROUND, [("U1", "4"), ("U2", "4")]),
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},
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)
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def test_pg_not_tied_to_en_is_warning():
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findings = check_power_sequencing(_dual("PGOOD", "EN_1V8"), _cons())
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assert len(findings) == 1
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assert findings[0].rule_id == "PS-SEQ-001"
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assert findings[0].status == "WARNING"
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def test_pg_tied_to_en_is_silent():
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assert check_power_sequencing(_dual("SEQ", "SEQ"), _cons()) == []
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def test_no_power_sequence_spec_skips_even_if_pg_open():
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assert check_power_sequencing(_dual("PGOOD", "EN_1V8", sequence=False), _cons()) == []
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