Check ImpedenceFinder against datasheet SI rules, not a dump table.

Each layout_rules SI requirement (diff/SE Z, skew, max length, spacing,
ref plane, vias, layer, return, series R) is one PASS/FAIL/MARGIN finding
with FACT and REQUIREMENT. USB/HDMI/PCIe/ETH/LVDS/DDR only; I2C GPIO CC
and analog REGN are skipped. No invented 90 Ω.

docs/piano-pcb-review.md

@@ -54,7 +54,10 @@ Mutex vs analisi e vs placement. SSE `pcb_*`. IDs `PCB-{ref}-{001}`. KiCad `/net
 | --- | --- |
 | PE-LAY-001…003 | pad/ref/hierarchy nets |
 | PE-PLC-001…004 | `layout_rules` numerici |
-| PE-SI-001 | `length_match` mm |
+| PE-SI-001 | `length_match` mm on USB/HDMI/PCIe/ETH/LVDS/DDR nets (not I2C/GPIO/CC) |
+| PE-SI-002 | ImpedenceFinder Zavg/min/max vs `impedance` window |
+| PE-SI-003…009 | max length, spacing, ref plane, vias, return, series R — each a datasheet number |
+| PE-SI-010 | HS bus measured, library has no SI FACT (not 90 Ω folklore) |
 | PE-PWR-001 | I_load + width; IPC solo con thickness e Tjmax |
 | PE-DRT-001 | Vop e Vrated, Vop > Vr → RULE ERROR |
 | PE-DRT-002 | 0.8 < Vop/Vr ≤ 1 → RISK MARGIN |
@@ -90,7 +93,22 @@ AI PCB: skip IC senza pintable (`run schematic review first`).
 | PE-ESD-001 | ESD connettore/USB | REVIEW se manca parte ESD |
 | PE-RET-001 | return HS senza via GND | REVIEW, non ERROR |
 
-**B — ancora aperta:** energy/thermal FEM; SI oltre skew mm; BOM↔PCB↔datasheet completo; SPOF; EMI oltre ESD REVIEW.
+**B — SI (shipped, gated):** ImpedenceFinder is **in the checks**, not only the impedance tab dump. Each datasheet SI requirement is one finding: PASS / FAIL / MARGIN + FACT / REQUIREMENT / source. Buses: USB D+/D−, HDMI, PCIe, Ethernet, LVDS, DDR. **Skip** I2C, GPIO, EN, analog REGN, USB CC (not 90 Ω pairs). No invented 50/90 Ω.
+
+Emmaforo USB verdict: if library has e.g. 90 Ω ±10% (81–99), Zavg ~88 Ω **PASS** on average and **MARGIN/FAIL** if min (~46 Ω) is outside the window; ~2.5 mm intra-pair skew **FAIL** only when `length_match` mm exists and 2.5 > limit. Without library Z, **PE-SI-010** INFO (insufficient) — not a 90 Ω ERROR.
+
+**B — still missing (close-out):**
+
+| Gap | Why it is not this slice |
+| --- | --- |
+| Thermal FEM / energy | PE-THM-001 is courtyard vias/pour vs P=I×drop, not a field solve |
+| SPOF | No single-point-of-failure / redundancy graph check |
+| BOM ↔ PCB ↔ datasheet chain | Pad-net + MPN library; no full three-way BOM audit |
+| ImpedenceFinder license | Vendored closed-form core (`vendor/impedancefinder`, SOURCE.md); **no LICENSE file in-tree** — confirm upstream license before commercial redistribution |
+| CPWG / field solver | OpenEMS export explicitly excluded from the vendor snapshot |
+| EMI beyond ESD REVIEW | PE-ESD-001 is REVIEW, not IEC 61000 |
+| SI extraction coverage | New `layout_rules` kinds need a re-extract (`model_version` 1.11.0); old library JSON has no Z/skew until pintable is refreshed |
+| Auto-place / pcbnew write-back | Fase C |
 
 **C — fuori:** auto-place, write-back pcbnew, unire i job, sshd/keys, PinScope identity/fork.