Check ImpedenceFinder against datasheet SI rules, not a dump table.

Each layout_rules SI requirement (diff/SE Z, skew, max length, spacing,
ref plane, vias, layer, return, series R) is one PASS/FAIL/MARGIN finding
with FACT and REQUIREMENT. USB/HDMI/PCIe/ETH/LVDS/DDR only; I2C GPIO CC
and analog REGN are skipped. No invented 90 Ω.

backend/periscopex/pcb_checks.py

@@ -174,13 +174,14 @@ def run_pcb_checks(
     constraints_map: dict,
     layout: LayoutGraph | None,
     plan: FunctionalGroupsReport | None = None,
+    impedance_nets: list[dict] | dict | None = None,
 ) -> list[Finding]:
     """Placement, SI, pad-net match, derating, hierarchy, timing, PI, ESD."""
     out: list[Finding] = []
     for name, fn in (
         ("pcb_net_match", lambda: check_pcb_net_match(graph, layout)),
         ("placement_check", lambda: check_placement(graph, constraints_map, layout)),
-        ("si_check", lambda: check_si(graph, constraints_map, layout)),
+        ("si_check", lambda: check_si(graph, constraints_map, layout, impedance_nets)),
         ("pcb_derating", lambda: check_pcb_derating(graph)),
         ("pcb_power_traces", lambda: check_pcb_power_traces(graph, constraints_map, layout)),
         ("pcb_via_current", lambda: check_pcb_via_current(graph, constraints_map, layout)),