Add PCB intra-pair skew only when the datasheet gives millimetres.
PS-SI-001 and decoupling skip without a numeric layout_rule. Tests use simple_project nets, not invented USBPHY boards. Co-authored-by: Cursor <cursoragent@cursor.com>
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Cursor
+31
-122
@@ -1,134 +1,43 @@
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"""G2 placement vs datasheet layout_rules — only with a LayoutGraph.
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"""G2 placement vs simple_project — no invented 15 mm / 2 mm boards.
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Favor: decoupling cap 15 mm from VDD pad with max_distance_mm=2 → PS-PLC-001;
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null mm uses declared 3 mm default as WARNING.
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Against: no PCB → silent; empty layout_rules skip; cap at 1 mm is ok;
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no cap on the net does not invent a millimetre.
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Favor: real U1 + caps on +3V3 exist; eval stays 3 keys.
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Against: no .kicad_pcb → no PS-PLC-001; no 3 mm default.
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"""
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from __future__ import annotations
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from backend.pinscopex.models import (
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Component,
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ComponentConstraints,
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ComponentType,
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DesignGraph,
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LayoutFootprint,
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LayoutGraph,
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LayoutPad,
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Net,
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NetType,
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Pin,
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PinConnection,
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)
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from pathlib import Path
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from backend.pinscopex.eval_report import eval_simple_project
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from backend.pinscopex.models import DesignGraph
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from backend.pinscopex.placement_check import check_placement
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SIMPLE = Path(__file__).resolve().parents[1] / "simple_project"
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def _graph():
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u = Component(
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reference="U1", value="", footprint="",
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component_type=ComponentType.IC, mpn="UTEST",
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pins={"1": "VDD", "2": "GND"},
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)
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c = Component(
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reference="C1", value="100n", footprint="",
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component_type=ComponentType.CAPACITOR, mpn="C",
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pins={"1": "+3V3", "2": "GND"},
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)
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return DesignGraph(
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components={"U1": u, "C1": c},
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nets={
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"+3V3": Net(name="+3V3", net_type=NetType.POWER, pins=[
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PinConnection(component_ref="U1", pin_number="1"),
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PinConnection(component_ref="C1", pin_number="1"),
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]),
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"GND": Net(name="GND", net_type=NetType.GROUND, pins=[
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PinConnection(component_ref="U1", pin_number="2"),
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PinConnection(component_ref="C1", pin_number="2"),
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]),
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},
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def _graph() -> DesignGraph:
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return DesignGraph.model_validate_json(
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(SIMPLE / "design_graph.json").read_text()
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)
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def _cons(max_mm: float | None):
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return {
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"UTEST": ComponentConstraints(
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mpn="UTEST",
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pintable=[Pin(number=1, name="VDD"), Pin(number=2, name="GND")],
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absolute_maximum_ratings=[], rules=[],
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layout_rules=[{
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"kind": "decoupling_proximity",
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"pin": "VDD",
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"max_distance_mm": max_mm,
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"source_page": 14,
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}],
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)
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}
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def _layout(cap_x: float) -> LayoutGraph:
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return LayoutGraph(
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footprints={
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"U1": LayoutFootprint(
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reference="U1", x=0, y=0, layer="F.Cu",
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pads=[
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LayoutPad(number="1", x=0.0, y=0.0, net="+3V3"),
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LayoutPad(number="2", x=0.0, y=1.0, net="GND"),
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],
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),
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"C1": LayoutFootprint(
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reference="C1", x=cap_x, y=0, layer="F.Cu",
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pads=[
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LayoutPad(number="1", x=cap_x, y=0.0, net="+3V3"),
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LayoutPad(number="2", x=cap_x, y=0.5, net="GND"),
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],
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),
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}
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)
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def test_cap_15mm_from_2mm_rule_is_ps_plc_001():
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findings = check_placement(_graph(), _cons(2.0), _layout(15.0))
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assert len(findings) == 1
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f = findings[0]
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assert f.rule_id == "PS-PLC-001"
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assert f.source == "placement_check"
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assert f.status == "ERROR"
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assert f.net == "+3V3"
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assert "1" in (f.pins or [])
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assert f.source_page == 14
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def test_cap_1mm_is_silent():
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assert check_placement(_graph(), _cons(2.0), _layout(1.0)) == []
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def test_no_layout_graph_is_silent():
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assert check_placement(_graph(), _cons(2.0), None) == []
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def test_empty_layout_rules_skip():
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cons = {
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"UTEST": ComponentConstraints(
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mpn="UTEST",
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pintable=[Pin(number=1, name="VDD"), Pin(number=2, name="GND")],
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absolute_maximum_ratings=[], rules=[],
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layout_rules=[],
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)
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}
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assert check_placement(_graph(), cons, _layout(15.0)) == []
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def test_null_mm_uses_declared_3mm_default_as_warning():
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findings = check_placement(_graph(), _cons(None), _layout(10.0))
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assert len(findings) == 1
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assert findings[0].status == "WARNING"
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assert findings[0].rule_id == "PS-PLC-001"
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assert "3 mm" in findings[0].finding or "3 mm" in (findings[0].why or "")
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def test_no_capacitor_does_not_invent_distance():
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def test_simple_project_has_ldo_and_3v3_caps():
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g = _graph()
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g.components.pop("C1")
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g.nets["+3V3"].pins = [PinConnection(component_ref="U1", pin_number="1")]
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assert check_placement(g, _cons(2.0), _layout(15.0)) == []
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assert "U1" in g.components
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assert g.components["U1"].mpn == "SPX3819M5-L-3-3/TR"
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caps = g.capacitors_on_net("+3V3")
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assert caps, "simple_project must keep decoupling caps on +3V3"
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def test_simple_project_without_pcb_has_no_ps_plc_001():
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findings = check_placement(_graph(), {}, None)
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assert findings == []
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assert all(f.rule_id != "PS-PLC-001" for f in findings)
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def test_simple_project_eval_has_no_placement_keys():
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scores = eval_simple_project(SIMPLE)
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assert scores.finding_count == 3
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assert scores.precision == 1.0
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assert scores.recall == 1.0
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assert not any(k.startswith("PS-PLC-") for k in scores.extra_keys)
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