Run ImpedenceFinder Z0 on routed signal nets during project analysis.
Pipeline samples PCB traces when stackup εr/h is present; power/ground are skipped. Named nets can be re-analyzed from the Impedance tab. Co-authored-by: Cursor <cursoragent@cursor.com>
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Cursor
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"""ImpedenceFinder analysis on specified nets — widths/stackup from the board.
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Favor: named net Z0 matches zsolver on the same w/h/εr/t.
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Against: empty net list; missing net; no stackup.
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"""
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from __future__ import annotations
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from pathlib import Path
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import pytest
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from backend.pinscopex.impedance import GeometryError
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from backend.pinscopex.impedance_traces import (
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analyze_specified_nets,
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analyze_where_needed,
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)
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from backend.pinscopex.models import (
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DesignGraph,
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LayoutDielectric,
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LayoutGraph,
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LayoutSegment,
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LayoutStackup,
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LayoutZone,
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Net,
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NetType,
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)
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from backend.pinscopex.parsers_kicad_pcb import parse_kicad_pcb
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from backend.vendor_path import ensure_impedancefinder
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ensure_impedancefinder()
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from impedancefinder import zsolver
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_H = 0.15
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_ER = 4.3
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_T = 0.035
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_W = 0.2
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_PITCH = 2.0
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def _layout() -> LayoutGraph:
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return LayoutGraph(
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segments=[
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LayoutSegment(
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start=(0.0, 0.0), end=(10.0, 0.0),
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width=_W, layer="F.Cu", net="SIG",
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),
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LayoutSegment(
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start=(0.0, 2.0), end=(4.0, 2.0),
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width=0.3, layer="F.Cu", net="OTHER",
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),
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],
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stackup=LayoutStackup(
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copper_layers=["F.Cu", "In1.Cu", "In2.Cu", "B.Cu"],
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dielectrics=[
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LayoutDielectric(name="prepreg_top", er=_ER, height_mm=_H),
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LayoutDielectric(name="core", er=4.4, height_mm=0.7),
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LayoutDielectric(name="prepreg_bottom", er=4.3, height_mm=0.15),
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],
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copper_thickness_mm=_T,
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),
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zones=[
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LayoutZone(
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net="GND",
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layer="In1.Cu",
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outlines=[[(-5.0, -5.0), (50.0, -5.0), (50.0, 5.0), (-5.0, 5.0)]],
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),
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],
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)
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def test_specified_net_z0_matches_impedancefinder_zsolver():
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rows = analyze_specified_nets(_layout(), ["SIG"], _PITCH)
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assert len(rows) == 1
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row = rows[0]
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assert row["net_name"] == "SIG"
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expect = zsolver.microstrip_z0(_W, _H, _ER, _T)
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assert row["z0_avg_ohms"] == pytest.approx(expect, rel=1e-6)
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assert row["z0_min_ohms"] == pytest.approx(expect, rel=1e-6)
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def test_only_specified_nets_are_analyzed():
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rows = analyze_specified_nets(_layout(), ["SIG"], _PITCH)
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assert [r["net_name"] for r in rows] == ["SIG"]
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def test_missing_net_is_error_not_invented_z0():
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rows = analyze_specified_nets(_layout(), ["NO_SUCH_NET"], _PITCH)
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assert rows[0]["error"] == "no segments on this net"
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assert "z0_avg_ohms" not in rows[0] or rows[0].get("z0_avg_ohms") is None
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def test_empty_net_list_is_silent():
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assert analyze_specified_nets(_layout(), [" ", ""], _PITCH) == []
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def test_no_stackup_raises():
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layout = LayoutGraph(
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segments=[LayoutSegment(start=(0, 0), end=(1, 0), width=0.2, layer="F.Cu", net="SIG")],
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)
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with pytest.raises(GeometryError, match="stackup"):
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analyze_specified_nets(layout, ["SIG"], _PITCH)
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_PCB_STACKUP = """(kicad_pcb (version 20240108) (generator pcbnew)
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(net 0 "")
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(net 1 "GND")
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(net 2 "SIG")
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(setup
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(stackup
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(layer "F.Cu" (type copper) (thickness 0.035))
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(layer "dielectric 1" (type core) (thickness 0.15) (epsilon_r 4.3))
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(layer "In1.Cu" (type copper) (thickness 0.035))
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(layer "dielectric 2" (type core) (thickness 0.7) (epsilon_r 4.4))
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(layer "In2.Cu" (type copper) (thickness 0.035))
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(layer "dielectric 3" (type prepreg) (thickness 0.15) (epsilon_r 4.3))
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(layer "B.Cu" (type copper) (thickness 0.035))
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)
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)
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(segment (start 0 0) (end 10 0) (width 0.2) (layer "F.Cu") (net 2))
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(zone (net 1) (net_name "GND") (layer "In1.Cu")
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(filled_polygon (layer "In1.Cu")
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(pts (xy -5 -5) (xy 50 -5) (xy 50 5) (xy -5 5))
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)
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)
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)
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"""
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def test_parse_stackup_and_zone_then_analyze_sig(tmp_path: Path):
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p = tmp_path / "board.kicad_pcb"
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p.write_text(_PCB_STACKUP)
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layout = parse_kicad_pcb(p)
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assert layout.stackup is not None
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assert layout.stackup.copper_layers[0] == "F.Cu"
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assert layout.stackup.dielectrics[0].er == 4.3
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assert layout.zones and layout.zones[0].net == "GND"
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rows = analyze_specified_nets(layout, ["SIG"], _PITCH)
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expect = zsolver.microstrip_z0(_W, _H, _ER, _T)
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assert rows[0]["z0_avg_ohms"] == pytest.approx(expect, rel=1e-6)
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def test_project_analysis_skips_power_and_runs_signal():
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graph = DesignGraph(nets={
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"SIG": Net(name="SIG", net_type=NetType.SIGNAL),
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"OTHER": Net(name="OTHER", net_type=NetType.POWER),
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})
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report = analyze_where_needed(_layout(), graph, pitch_mm=_PITCH)
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assert report["skipped"] is None
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names = [r["net_name"] for r in report["nets"]]
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assert names == ["SIG"]
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expect = zsolver.microstrip_z0(_W, _H, _ER, _T)
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assert report["nets"][0]["z0_avg_ohms"] == pytest.approx(expect, rel=1e-6)
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def test_project_analysis_skips_without_stackup():
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layout = LayoutGraph(
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segments=[LayoutSegment(start=(0, 0), end=(1, 0), width=0.2, layer="F.Cu", net="SIG")],
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)
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report = analyze_where_needed(layout, None, pitch_mm=_PITCH)
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assert report["nets"] == []
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assert report["skipped"] == "no stackup"
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def test_pipeline_writes_impedance_nets_for_signal(tmp_path: Path):
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import json
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from backend.services.pipeline import _write_impedance_nets
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class Ws:
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def local_path(self, rel: str) -> Path:
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return tmp_path / rel
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layout = _layout()
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(tmp_path / "layout_graph.json").write_text(layout.model_dump_json())
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graph = DesignGraph(nets={
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"SIG": Net(name="SIG", net_type=NetType.SIGNAL),
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"OTHER": Net(name="OTHER", net_type=NetType.POWER),
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})
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_write_impedance_nets(Ws(), graph)
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data = json.loads((tmp_path / "impedance_nets.json").read_text())
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assert [r["net_name"] for r in data["nets"]] == ["SIG"]
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def test_get_impedance_nets_without_run_is_empty(tmp_path: Path):
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from fastapi.testclient import TestClient
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from backend.main import app
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from backend.services.storage import LocalStorageBackend
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app.state.storage = LocalStorageBackend(tmp_path)
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client = TestClient(app)
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pid = client.post("/api/projects", json={"name": "z0"}).json()["id"]
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body = client.get(f"/api/projects/{pid}/impedance/nets").json()
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assert body["nets"] == []
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assert body["skipped"] == "not run"
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