Ship Fase B slices: hierarchy, derating bands, timing, PI, ESD/return.

ERROR stays only for RULE+MANDATORY. Hierarchy walks component→pin→net→block.
Derating is PASS/MARGIN/RISK from Vop/Vrated. Timing and PI skip without numbers.
ESD and HS return path are REVIEW, not RULE ERROR.

tests/test_finding_engine.py

@@ -52,6 +52,56 @@ def test_llm_review_is_never_rule():
     assert f.finding_class == "REVIEW"
     assert f.facts
     assert f.requirement
+    assert f.status == "WARNING"
+
+
+def test_review_and_risk_cannot_stay_error():
+    review = Finding(
+        designator="U1",
+        finding="PowerPAD vias",
+        why="layout note",
+        status="ERROR",
+        source="pcb_review",
+        facts="0 vias under U1",
+        requirement="datasheet PowerPAD",
+        source_quote="Connect the thermal pad with vias to GND.",
+        evidence_status="SUFFICIENT",
+    )
+    complete_finding(review)
+    assert review.finding_class == "REVIEW"
+    assert review.status == "WARNING"
+
+    risk = Finding(
+        designator="C1",
+        finding="high utilization",
+        why="Vop near Vr",
+        status="ERROR",
+        rule_id="PE-DRT-002",
+        source="pcb_derating",
+        evidence_status="SUFFICIENT",
+        facts="3.0 / 3.3 V",
+        requirement="utilization band",
+    )
+    complete_finding(risk)
+    assert risk.finding_class == "RISK"
+    assert risk.status == "WARNING"
+
+
+def test_mandatory_rule_stays_error():
+    f = Finding(
+        designator="U1",
+        finding="NC tied",
+        why="NC must float",
+        status="ERROR",
+        rule_id="PE-NC-001",
+        source="nc_pin_check",
+        facts="NC on GND",
+        requirement="NC pins must not be connected.",
+        evidence_status="SUFFICIENT",
+    )
+    complete_finding(f)
+    assert f.finding_class == "RULE"
+    assert f.provenance == "MANDATORY"
     assert f.status == "ERROR"