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Ship Fase B slices: hierarchy, derating bands, timing, PI, ESD/return.

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ERROR stays only for RULE+MANDATORY. Hierarchy walks component→pin→net→block.
Derating is PASS/MARGIN/RISK from Vop/Vrated. Timing and PI skip without numbers.
ESD and HS return path are REVIEW, not RULE ERROR.
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michele
2026-09-20 09:35:04 +02:00
parent facbaa2305
commit 342792df2d
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What's new in Periscope.
## 2.33.0 — 2026-09-20 — Fase B: hierarchy, derating bands, timing, PI, ESD/return
Usable slices (not a platform): component→pin→net→block inventory, capacitor PASS/MARGIN/RISK from Vop/Vrated, RC/strap timing only with numbers, local vs bulk PI, ESD and HS return as REVIEW.
- [Fixed] `complete_finding` clamps ERROR unless `finding_class=RULE` and `provenance=MANDATORY` (LLM REVIEW cannot stay ERROR).
- [New] `hierarchy.json` + `PE-HIER-001` dangling IC pins.
- [New] Derating table `stress` PASS/MARGIN/RISK; findings `PE-DRT-001/002/003`.
- [New] `PE-TIM-001/002` skip without R/C and t_reset or Vih/Vil.
- [New] `PE-PI-001/002` local vs bulk; distance only with `layout_rules` mm.
- [New] `PE-ESD-001`, `PE-RET-001` are REVIEW, never RULE ERROR.
## 2.32.1 — 2026-09-20 — PCB Action on card + parsed geometry in AI context
Finding cards always show an **Action.** sentence (`action`, else `recommendation`, else a default). PCB AI context now includes vias under the footprint, copper thickness, nearby trace widths, courtyard, and keepout polygons from `.kicad_pcb`.